W65C02S, Z80, 80C31 or other legacy processor?

It's really not a viable candidate, sorry. Not COTS enough, OTP, not viable.

Reply to
zwsdotcom
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I am not going to argue what's COTS or not. You can disable internal OTP ROM and use external ROM. There are six Chip Select lines (CS0 for internal OTP ROM). The other 5 CS can be mapped to external address space of 16K out of 16M (24 address bits). But I haven't figure out how to access more than 64K of the 6502 mode yet.

Reply to
linnix

I tried using the spi output on the atmega48 series for a vga output but found the processor clock was stopped when the spi was outputing data. This might have been a skipped clock pulse for the processor each step in the spi shift register, since they were probably both at the same speed. Be warned there may be trouble generating 40 characters. Be warned also that I didn't check all possibilities at the time. Anyway, using an atmega for a vga generator might merit an early verification.

Hul

snipped-for-privacy@gmail.com wrote:

Reply to
dbr

ut

????!! Are you using DMA? I was not planning it.

It is really a very well-researched technique. Example - he was limited by RAM in the particular part he chose.

The way I intend it to work is that the mega8 will remember in EEPROM which display mode was last selected. (A different mode can be selected by holding down a key at POR, or under programmatic control from the main micro). It will output a possible subset of a large virtual screen to the selected display device.

The virtual screen will always be 40x24, and in either NTSC or VGA mode the entire virtual screen is visible. In LED mode, the first 10 bytes of the display buffer will map to the LED digits.

I will also support connection to an external 2-line Hitachi- compatible LCD, which will occupy the upper LH corner of the virtual display.

Reply to
zwsdotcom

That link only mentions 20 chars in VGA ? To get 40 wide in x8 font, you will need a 25MHz+ AVR - an ATXmega might make that ? ( The venerable Mega8 is only 16MHz - Mega88 nudges to 20MHz ATMega168P is probably a better sweet-spot part.)

Atmel claims this of the Xmega ".. announced its industry leading XMEGA=99 microcontroller was awarded the 2008 Product of the Year by Electronic Products' Magazine. Since its introduction in early 2008, there have been over 400 design wins to validate this award."

I have no idea where all those claimed design-wins are getting their silicon, everywhere I look claims "No Stock" !!?

-jg

Reply to
-jg

Because he was RAM-limited.

Err... check that calculation. The nominal dot clock for a 640x480 mode is 25MHz. For 40-column x8 pixel text I only need 12.5MHz; actually less if I get freaky with the porches.

Oddly enough the 169P is cheaper. It's the same silicon in fact, but the 168P has the LCD controller either disabled or untested.

Obviously the people who designed it in are eating all the production capacity :)

(Seriously, I feel your pain. Atmel is one of those vendors where I don't design in the part until I see it at Digi-Key, in stock).

Reply to
zwsdotcom

?? - he got more width in PAL mode, so RAM is no the issue here. Dot clock is.

Yes, but the SPI max clock is /2 so your 12.5MHz needs a 25MHz device.

-jg

Reply to
-jg

Hmm. Let me look at that. I thought I'd run the calculations and made it work. Getting a bit sleepy to make good sense of it all tonight :)

Reply to
zwsdotcom

Sleepy ? it's mid afternoon here ;)

-jg

Reply to
-jg

Depends on where he is. I have posted here from opposite side of the Earth myself.

Reply to
linnix

Given this needs 25MHz+, the next step would be 27MHz (PAL./NTSC common)

- My Candidate devices would be - (both new), similar prices $3 +/-

10%

ATXmega 32MHz 32K/4K- prices are up, so must be close (even if not in stock yet..)

C8051F507 50MHz 32K/4K - smaller package, would allow 40MHz or 40.5MHz clock.- F507 is in stock at Distis.

-jg

Reply to
-jg

If you don't need full color, you can get by with lower frequency. Early computers only support 8 to 16 colors (3 to 4 bits) anyway. You can add a $1 CPLD shift register for serialization.

Raw MHz doesn't mean a lot. Will you be able to shift one bit per Hz?

Reply to
linnix

My vote would be for a $1 CPLD and a $1 SPI SO8 SRAM, == small PCB area impact (very important), small cost impact, but a device with more 'cred' results.

Part of the CPLD price can offset into a cheaper uC.

You can kludge part way, with a LVC257 driven from SPI_DO. but why do the half-step ?.

I'd say something more than simple 1 bit monochrome is important, as something like a syntax highlighting editor becomes easy then. Does not need to be colour, just greyscale.(or GreyScale/RGB options)

and I'd add the AT32UC3D, (when it becomes more real....)

Most devices have an SPI clk of SYSCLK/2, that gives 16 clocks to get your ducks in a row per SPI load. With a CPLD, the raster SRAM- Video bypasses the MCU, but a fast clock is still important to load the SRAM in the blanking times.

-jg

Reply to
-jg

,
u

not

z
?

If you are feeding digital video directly out of the CPU, it can't be too hard. The Z80 based Sinclare ZX did it over 20 years ago. How did they do it?

Rick

Reply to
rickman

He (jg) shows up as posting on "Sun, 29 Mar 2009 18:52:56 -0700 (PDT)", which makes no sense for mid-afternoon. He must be posting from Hawaii via google, where the receiving station is on PDT and applying its date to the message. One more of the penalties for using a non-receiver such as the google system.

--
 [mail]: Chuck F (cbfalconer at maineline dot net) 
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Reply to
CBFalconer

So did the Apple IIe, among others. In fact, what we are currently dealing with is a single chip IIe+. The 65C02 core with 32K video ram can already drive passive STN LCD panel with 1 bit or 4 bits serial data bus output. We are asking them to supply a version with direct

256 segments and 128 commons drivers (exact size is still TBD). Together with a $5 OLED screen, we have much of the IIe power for under $10.

By the way, the OLED screen can be built directly on flexible PCB and bonded with a 500+ pads die. The OP asked if there are modern devices for 6502. The answer is definitely yes, we just don't see or hear about them much.

Reply to
linnix

nt,

z

You

if not

MHz

Hz?

The Sinclair's had a Logic Array helping on the video, "as built around a semi-custom Ferranti ULA " and also had a TV only, and low 32 characters wide by 24 high.

- Still, it WAS very impressive for a 3.25MHz CPU clock & 1K base ram,

8K ROM, even if it used many compromises to get there.. VGA speeds had not even been thought of...

In many ways, my suggested approach is similar: A small CPLD to assist the uC, the luxury of very recent 32KB SO8 memory, and a 'small' [32KF/4KR] 32-50MHz uC - and most of the compromises are gone...

-jg

Reply to
-jg

The testing didn't use DMA - if the atmega48 has that capability, I'm unaware of it. The Greek fellows results were/are impressive but, if memory serves, the lines were crowded; they started at the rightmost extreme and stopped a hint after the leftmost. In tv parlance, the "front porch" and "back porch" weren't given fair space. Checking to see if that example used a 16 mhz clock or 20 mhz could be worthwhile. If 16 mhz was used, 20 would provide leeway.

Hul

snipped-for-privacy@gmail.com wrote:

Reply to
dbr

No they didn't. The Apple II line (II, II+, //e, and //c, at least), had dedicated video drivers, and did not rely on the CPU at all. They did have somewhat odd addressing, and ran memory at twice the CPU speed to that the video and CPU sections were able to access the memory on alternate cycles. They also used the continuous video accesses to satisfy the DRAM refresh requirements. And they slightly overclocked the CPU so that they could synchronize it with the video clock (the whole system ran off a 14.31818MHz clock, divided down by

14 for both the CPU and video memory byte access).
Reply to
robertwessel2

You are thinking of the Sinclair ZX81. The ZX80 (not the spectrum I initially mentioned) used only the Z80 and some TTL logic. There was no ASIC of any sort. I remember I either got schematics or traced out the circuit manually and was surprised to find that they were using an interrupt one the line retrace signal and then used software to output the data for the display.

At least, that is what I recall. It does make sense when you realize that when the unit did anything that needed more than 10% of the CPU, the display actually stopped!

Rick

Reply to
rickman

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