VME and Big Endian

Hello, I want to access from a Big endian CPU, a VME bus peripheral card. Let's say for example, I want to write a value that ends up in a register on the card, at address 0x2, in the register I want to have

0x1234, in other words, in bits 0-7 of the register I want to have 0x34, and in bits 8-15, I want to have 0x12. And suppose I want to do this with a 16-bit bus write operation from the CPU. Question is, what value should I write, and where?

OK, why am I describing such a trivial problem at such great length? :)

Well I thought this was trivial, I would just write 0x3412, and the address is the same 0x2. Why? Well, every child in kindergarten knows:

VME bus is 16-bit bus and uses big-endian byte addressing within the bus width. So if I wanted to write a byte to bits 0-7 of the register, I would have to use address 0x3, and to bits 8-15, address

0x2, but since I want to write the whole word, then the address does not change. And that is all that VME bus matters. CPU being big endian in the way stores words, I have to write 0x3412. In other words, if I write 0x3412, 0x34 goes out on the system bus, on data lines 0-7, and 0x12, goes out on lines 8-15, and that is where they end up on the VME bus as well.

Right? Wrong! Checking on the hardware, it seems wrong - I have to write 0x1234. Why in the world would that be????

Well, perhaps I think, this is the way to think about it. When I tell the big endian CPU to write 0x1234 at 0x2, it says, OK, I will put byte 0x12 at byte address 0x2, and byte 0x34 at byte address 0x3. It's as if the CPU does not just write the 16-bit value in its own way, into the address provided, but - it actually breaks down into bytes, and writes individual bytes into their own addresses. And then the byte address 0x3, that is the bits 0-7 on the bus, and byte address 0x2, that is the bits 8-15. In other words, it's as if the CPU had knowledge of the final bus the stuff goes on, and puts data on the data lines accordingly, or perhaps somewhere in the middle, the data lines are swapped. This seems really weird, but I have no other explanation.

QUESTIONS:

  1. Is this the right explanation?

  1. Then what to do with the little endian CPU (which I don't have access to right now) - does it also break down the word into two bytes and then decides what address to write each individual byte?

thank you for any insight, Mark Galeck

Reply to
Mark_Galeck
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yes, I answered myself - the data lines must be swapped by the VME bus bridge, that is the only explanation, one can see that has to be the case, by considering how byte-wide quantities are written.

Reply to
Mark_Galeck

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