TFT contrast problem

How did you configure timing? We did a 13706 using epson's configuration utility and found that will not output the correct value for the pixel clock divider, resulting in pck=clkin. Hand check all output values from that utility if you use something simular.

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Thanks for reply. I've used Epson's config utility too. CLKI = 6,25MHz pixel clock = CLKI, frame rate = 50Hz (512 clocks per line). I've measure all signals by scope and it's ok. I think there is some problem with panel I have only one panel for my prototype board. Is there some possibilit that panel was degraded during firmware developement? Panel is 24 bit an s1d13705 12 bit only - I have R G and B LSBs grounded.

You say you are looking at a narrow color bars but the height is unlimited. So you have about 20 pixels of color and no activity on rest of the panel? Is your memory mapped correctly? I would make sure the configuration is correctly set. I have worked on S1D13A05 and you will have to check the signals on the scope to make sure all the timings are right. The data sheet for that module has timing diagrams and that will help you set up the correct values. The configuration utility was not able to give us precise values.

Suresh M. Shenoy

Epson

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No, panel is mapped correctly - I'm able to draw any pixel i want. Th problem is following: If I draw very short horizontal line (i.e. 20px long the color of the line is correct. But if the line is bigger (100px o more) color starts to change - It's loosing contrast. If the line is mor than 200px long color of the whole TFT panel row starts to be inverted. Th result is that It's not possible to fill display with black colour becaus black changes to white. It's possible to draw only very narrow black bar from top to bottom (over all 240 lines), but when width is increasing blac changes to grey. I'll will make and upload some photos to my FTP server.

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Here are some photos. Sorry for bad quality - made by mobile phone. Her you can see, how color changes with number of painted pixels on line.

And here is TFT datasheet There is 512 clocks per line (in datasheet). Isn't it too much? Is ther some possibility that one line is driven for a very long time (all timing were measured by scope and are OK - PCLK 6.25MHz, line frequency 12kHz frame rate 50Hz)? I can post here register setup of S1D13705 and TFT panel Thank you for any help.

This is only a guess, I am not at all familiar with your hardware. I suspect that something in the display is AC coupled, and trying to restore the average illumination level. From your description that something is line based.

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I see the problem. Could you verify the value at these memory locations? Make sure you are reading the same values you write. If for instance FF is black in your color pallete and you write it to mem loc x10 then when you read it, it should be x10. If not then there is an issue. If you confirm that the data are the same then i suspect panel might have some other issue.

You also mentioned something regarding 12bit s1d13705 and 24bit chip. I think you should investigate this is set up right. There are some bit shift mechanism to get the correct color. If this is set wrong we could also notice the behavior you are seeing.

Suresh M. Shenoy