Spikes in digital logic outputs on startup?

Indeed, one needs to know what V is fully off for the fet, and down to what V the logic will work correctly.

Sitting here thinking about it I'm realising that in the other scenario the fet gate could reach +0.6v relative to its other electrodes, as the V on those other trodes will drop during supply rail drop. Depends on your chip outputs though, chips that have V_out_max thats well below the + rail wont get the fet into that situation.

The power rail has a reservoir cap which limits the rate at which its V drops, so that the fet's diode has a controlled discharge rate into the power rail: thus there is no issue with diode speed, or lack of. If the power rail V drops a lot faster than that then there is a substantial fault, and things have already become uncontrolled.

On another tack, I guess your basic old RC on a reset pin is good in that it much reduces the frequency of misbehaviour, but bad if you're relying on it to work every time. So that's not so much bad circuitry, as circuitry that doesnt do what its popularly expected to do, ie often misused circuitry. In military tronics, yes, bad, but in consumer tronics not necessarily.

Regards, NT

thread.

I have, and it makes no difference. It's still lame.

Steve