Re: RTOS for ARM Cortex M1

Sorrry for the delayed reply..

Using the 3M part. Will have at least 512M.

In the interim I happened across this post on Keil's website.

formatting link

It basically says that because Actel has not implemented 'OS extensions' that no OS will run on this core. I also found that Actel has ported a v3, which does support OS extensions, to their SmartFusion line. --which I cannot use because it is not rad-tolerant. So now, I'm trying to get them to port their v3 core to the ProASIC3 3M part. No word yet on if or when they will fix this.

Can anyone enlighten me on exactly what OS extensions are? and whether there is a way around the issue (other than having actel fix the IP core)?

thanks!

Does anyone know of either a free or commerical RTOS that supports ARM Co=

rtex M1? I'm finding that some vendor's websites claiming support are inacc= urate.

> Looking for RTOS with filesystem and drivers to support a SoC implentatio=

n in an Actel FPGA...

> Any recommendations?

How much memory are you going to have? If you have a couple of

256Mx16, you might be able to run Linux.

Are you using the 600K or 3M part?

--------------= Posted using GrabIt =----------------

------= Binary Usenet downloading made easy =---------

-= Get GrabIt for free from

formatting link
=-

Reply to
bo
Loading thread data ...

Good for you. I am using 600K A3 and 32Mx32 SDRAM

that no OS will run on this core. I also found that Actel has ported a v3, = which does support OS extensions, to their SmartFusion line. --which I cann= ot use because it is not rad-tolerant. So now, I'm trying to get them to po= rt their v3 core to the ProASIC3 3M part. No word yet on if or when they wi= ll fix this.

ere is a way around the issue (other than having actel fix the IP core)?

Yes, license the source and patch it.

The link

formatting link
said it all:

1) 2 stacks pointer (leaving only 1 stack pointer). 2) The SVC assembler instruction for software interrupts (protected/ user mode). 3) System timers - for systick?> 1) & 2) stops you from having supervisor mode. 3) can probably be work around with additional resources to implement a timer.
Reply to
linnix

' that no OS will run on this core. I also found that Actel has ported a = v3, which does support OS extensions, to their SmartFusion line. --which = I cannot use because it is not rad-tolerant. So now, I'm trying to get th= em to port their v3 core to the ProASIC3 3M part. No word yet on if or wh= en they will fix this.=20

there is a way around the issue (other than having actel fix the IP core)= ?=20

You can run an RTOS on small 8 bit devices, that definitely don't have the undefined 'OS extensions'. All you need is to find an OS that has been ported, or pay somebody to port it for you.

Some CPU's have additional features that assist in the writing of an RTOS, some are just CPU's. You can run an RTOS on both, one will just be easier to write than the other. FreeRTOS runs on 25 different cores (thats cores as in architectures, not devices), believe me they don't all have OS extensions.

Regards, Richard.

  • formatting link
    Designed for Microcontrollers. More than 7000 downloads per month.
  • formatting link
    Certified by T=DCV as meeting the requirements for safety related systems= =2E
Reply to
FreeRTOS info

' that no OS will run on this core. I also found that Actel has ported a v3= , which does support OS extensions, to their SmartFusion line. --which I ca= nnot use because it is not rad-tolerant. So now, I'm trying to get them to = port their v3 core to the ProASIC3 3M part. No word yet on if or when they = will fix this.

there is a way around the issue (other than having actel fix the IP core)?

They should have said no protected mode OSs.

ProASIC3 with M1 soft core is for smaller devices.

SmartFusion with Cortex M3 hard core is for bigger devices and bigger OSs.

Reply to
linnix

that no OS will run on this core. I also found that Actel has ported a v3, = which does support OS extensions, to their SmartFusion line. --which I cann= ot use because it is not rad-tolerant. So now, I'm trying to get them to po= rt their v3 core to the ProASIC3 3M part. No word yet on if or when they wi= ll fix this.

ere is a way around the issue (other than having actel fix the IP core)?

of either a free or commerical RTOS that supports ARM Co=3D

cc=3D

io=3D

Check out Segger embOS. Should do what you want.

An Schwob

Reply to
An Schwob in the USA

This is not a bug that can be fixed, it is an implementation option of the processor core that Actel apparently chose to disable. The OS extensions in C-M1 are not essential to execute an OS on this CPU, but they can help implementing one.

The OS extension comprises of:

  1. A second stack pointer to implement two separate stacks for tasks and OS

  1. The SysTick timer which serves as a global time base for scheduler.

  2. The SVC/PendSV exceptions to request OS services.

Best regards

-- Marcus Harnisch Senior Consultant

DOULOS - Developing Design Know-how VHDL * SystemC * Verilog * SystemVerilog * e * PSL * Perl * Tcl/Tk ARM Approved Training Centre (ATC)

Doulos Ltd., Central European Office, Garbsener Landstr. 10, 30419 Hannover Tel: +49 (0)511 2771340 mailto: snipped-for-privacy@doulos.com Fax: +49 (0)511 2771349 Web:

formatting link

This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

Reply to
Marcus Harnisch

No. It means no user mode. By default the CM1 runs in a supervisor alike mode.

An RTOS does not need supervisor/user mode to allow writing safe software. It is a matter of clean design (=> direct message passing).

--
42Bastian
Do not email to bastian42@yahoo.com, it's a spam-only account :-)
Use @monlynx.de instead !
Reply to
42Bastian Schick

It seems that for a clean context switch, the Cortex m needs a software interrupt (be it then called a supervisor call or something else).

The ARM7TDMI method of switching via PSW to IRQ or SVC mode is not available in Cortex.

--

Tauno Voipio
tauno voipio (at) iki fi
Reply to
Tauno Voipio

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.