We are currently using the NXP PCA9535 components in a set of 4, all of course wired with different hardware addresses.
Out of the 4 components, 3 are used in output mode only (addresses 0 to 2), 1 in input mode only (address 3).
The interrupt line goes active as expected on the "input" PCA9535 (address 3) when a change occurs on one or more of the input lines to the chip.
The "output only" components (0 to 2) were also actually read/written back to perform a read modify/write back operation on the output port bits.
AND believe it or not, the interrupt line of chip n=B0 3 IS reset when reading chip 0 for instance.
Captures made on a state analyzer indicate clearly that the components are correctly driven for write and read sequences, and that the INT/ is really reset at the end of the reading of ANOTHER chip than the one activating the interrupt.
It looks as if the chip did not care about verifying if the address in the first byte received for the read effectively matches its own hard wired address !!!
Otherwise said, any read on any address would reset the Interrupt request ???
Help. If our conclusions are correct, this is enormous... Hope we are wrong.