- Is AL422B still in production?
- As for Read Operations the datasheet notices:
"When the new data is read, the read address should be between 128 to 393,247 cycles after the write address, otherwise the output may not be new data."
Does it mean that data is pushed into the FIFO in 128 bytes sized blocks?
- As for the Single Field Write with Multiple Read Operation:
"In order not to violate the 128 cycles of write to read delay latency rule, the write address (pointer) needs to be reset to 0 for the coming multiple read operations so that FIFO can provide the expectant data at DO bus."
Does it mean that using the chip for single frame captures is hard ?