Hi,
I was wondering whether there are any PPC405-specific memory layout constraints.
I am trying to get OSE5.1 (some embedded RTOS) running on a PPC405 embedded system. It went well on a dedicated evaluation board (Memec VP20, VirtexII-Pro), but "moving" to the target system failed so far.
There is a 32MB SDRAM located at 0xFC000000 - 0xFDFFFFFF. The OS is configured to use that memory starting at 0xFC900000. The gap between 0xFC000000 and 0xFC900000 is used for the exception vector area and system start up logging.
Since the original OS configuration expected the SDRAM at 0 -
0x01FFFFFF, and thus vector base is at 0, I was wondering if 0xFC000000 is still OK? I read that address has to be 64k-aligned.Is there a default setting for the PPC405 that the exeception area has to start at 0?
Thanks in advance
Florian
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