OSE5.1/PPC405 memory layout constraints?

Question

Hi,I was wondering whether there are any PPC405-specific memory layout constraints.I am trying to get OSE5.1 (some embedded RTOS) running on a PPC405 embedded system. It went well on a dedicated evaluation board (Memec VP20, VirtexII-Pro), but "moving" to the target system failed so far.There is a 32MB SDRAM located at 0xFC000000 - 0xFDFFFFFF.The OS is configured to use that memory starting at 0xFC900000.The gap between 0xFC000000 and 0xFC900000 is used for the exception vector area and system start up logging.Since the original OS configuration expected the SDRAM at 0 - 0x01FFFFFF, and thus vector base is at 0, I was wondering if 0xFC000000 is still OK? I read that address has to be 64k-aligned.Is there a default setting for the PPC405 that the exeception area has to start at 0?Thanks in advance	FlorianXPost to  &

Dimiter Popoff · Accepted Answer

Florian,without knowing OSE5.1 but with the experience of having writtenat least one (pretty fat) OS I would speculate that the problem isnot having memory at 0. You can relocate the vectors, sure, butit could well be that the OS relies on some addresses in the lowest64k for sort of "direct" access (I do it and if you deprive DPS of theRAM at 0 just like that all you can expect is a complete mess). If you could somehow capture whether it attempts such accessesthis might be revealing. Again, this is only speculation based only on related, not directexperience so please take it with due caution.Dimiter------------------------------------------------------Dimiter Popoff               Transgalactic Instruments

Florian Boelstler · Answer

Hi,I also configured the OS regarding the relocated vectors (who knows whether there is something hard-coded left).Nevertheless I will hopefully get a new hardware design in a while, that   matches the address map of the evaluation board.   Florian

Bartjan van der Meer · Answer

Hai,Regarding the ppc405: this architecture comes with the Exception Vector Prefix Register. Your bootstrap, the code that inits the board, should set this register conform the physical memory.Ose (5.1) has a config parameter that enables you to tell the kernel where the exception table ought to be. In your case equal to the EVPR, but perhaps there is no need to configure it (i.e. the kernel might just take the EVPR setting).Regards,Bartjan

OSE5.1/PPC405 memory layout constraints?

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