NXP Cortex M0 cores - an opcode-pruned subset of M3. Needs custom tool flows.
- 50 MHz PLL Cortex-M0 processor with SWD/debug (4 break-points) * 32 Vectored Interrupts; 4 priority levels; Dedicated Interrupts on up to 13 GPIOs * Fractional Baud UART, 1 or 2 SPI, I2C (FM+); 2 16-bit and 2 32- bit timers with PWM/Match/Capture * 12MHz Internal RC Oscillator with 1% accuracy over temperature and voltage * Power-On-Reset (POR); Multi-level Brown-Out-Detect (BOD); 10-50 MHz Phase-Locked Loop (PLL) * 8-channel high precision 10-bit ADC with =B11LSB DNL * Up to 28 or 42 fast 5V tolerant GPIO pins for HVQFN33 and LQFP48 respectively, high drive (20 mA) on select pins * Single 1.8 =96 3.6V power supply; over 5kV ESD for rugged applications
Missing? :
No quadrature mode in Counters ? No mention of LIN bus / autobaud support ?
Some nice details Fully deterministic exception handling timing behavior =96Always takes the same number of cycles to handle an exception =96Fixed at 16 clocks for no jitter
and a mangled comment about Jump times ?
-jg