I know this is implementation specific but to make it a little less ambiguous let's deal with an XScale or any ARM core for that matter. Under what conditions would you _miss_ interrupts? Let's say I have a UART that only generates one interrupt to the interrupt controller but the source of this interrupt within the UART can be due to various reasons. For example, maybe there is a FIFO overflow or maybe there is some sort of error condition, etc which each can cause the one interrupt line to the interrupt controller to be asserted.
1)First, if interrupts are disabled in the UART and some condition that can generate an interrupt arises, such as an empty FIFO, and I then enable interrupts in the UART sometime later, will an interrupt be generated then at this time if the FIFO is still empty?2) If the FIFO overflows and I get an interrupt and I am in the interrupt service routine, and interrupts are globally disabled by the processor, if while I am in the ISR another condition in the UART causes an interrupt, will this cause me to reenter the ISR once I return after servicing the FIFO overflow? Does this have anything to do with where in the ISR I clear the status flag in the UART register that indicates a FIFO overflow, i.e. clearing at the start of the ISR or right before I return? I have always heard to clear the flag at the start of the ISR, but I am not sure the exact reason.
3) With regards to missing interrupts, would this only happen if for example I have a timer set to interrupt me every 1 ms but I am in an ISR for a UART, for example, that takes longer than 1 ms to execute?Thanks.