For all the DAC-experienced, I need to interface a Cirrus Logic DAC (CS4341) to an AT91RM9200 which has the necessary three-wire I2S interface embedded (SSC). The DAC also requires that the LRCK (sample frequency) must be synchronously derived from a master clock 'MCLK', which can be 256, 384, 512 times the sample rate (among other choices). I have been advised that the LRCK (sample frequency) is internally derived (divided) from the CPU's 'MCK', but still there doesn't seem to be any way to pull an appropriate signal from the CPU.
The sample rate may be flexible, as I just hope to get it working at any frequency, eg.256x: LRCK = 48kHz | 44.1kHz (one of the three I2S signals) MCLK (12.288MHz) | (11.2896MHz)
or 384x: LRCK = 48kHz | 44.1kHz MCLK (18.4320MHz) | (16.9344MHz)
(FYI, I am working with the CSB637 and CSB937 single board computer, and Microcross GX-linux BSP)
Any help is much appreciated.