i2c repeater

Hi,

I wanted to implement an i2c repeater in software. Actually, Not a complete i2c but only one master to one slave repeater. I thought I can use a microcontroller and connect two I/Os to the master and 2 more to the slave in open drain fasion. So I need to reflect the clock from the master to the slave and the data to/from the master from/to the slave, depending on the direction. I thought I would use some kind of buffering (1 bit or 8 bit).

Does anyone did somthing like that? Is it possible? What tricks to use? I know of few problems in the way, such as:

1) If I'll use one bit buffer the master will wait for Akn after the 8th bit while the slave only got the 7th. 2) If I'll use 8 bit buffer, what to do when the last byte of a transaction was corrupted? 3) What is the best way to handle slatting?

Thank a lot for any help. Nadav.

Reply to
Nadav
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I've done this and planning on making it public on my website soon. The limitations are:

- No clock-stretching from the slave-side is allowed (clock is allways driven by the master)

- Masters can only be on the 'master' side. (Slaves can be on either side.)

- Speed: I could get it up to about 50kHz clock rate on an AVR. Might get higher if you optimize code by hand.

You don't have to actually understand the protocol and know when to drive which way: you can write code that monitors both the master and the slave side data lines and reflects the correct values back and forth. That way there's no buffering needed.

Regards, Andras Tantos

Reply to
Andras Tantos

Parden my ignorance, but why is a microcontroller needed for an I2C repeater? Can't you just split the signal in two with added drivers so the signal isn't degraded?

Reply to
Gary Kato

Why not use a Philips PCA9515A, a I2C bus repeater in a SO-8 package. Only $0.70....

Meindert

Reply to
Meindert Sprang

It's easy to do with a few FETs. Philips has an application note about it somewhere: the data (and clock) line is a float-up-pull-down, so by using the intrinsic diode across the Drain/Source, one "side" can pull down the other; and by using normal FET behavior, the other side can pull down the one. The same circuit can be used for voltage-level mapping (like 3v to 5v) and isolation (for low power)

From memory (which is probably wrong), you (I think) ground the Gate of one N-Channel FET (Enhancement, MOS) and have one side of the SDA/SCL line pull the other one "down" through the FET's intrinsic diode. The other side pulls the one side down by pulling the source down, thus making Vgs sufficiently high for Ids to flow.

You have a pullup on each segment and each pullup can pull to a different Vcc.

Richard [in PE12]

Reply to
Endymion Ponsonby-Withermoor III

snipped-for-privacy@aol.com (Gary Kato) wrote in news: snipped-for-privacy@mb-m24.aol.com:

I'd say not, because I2C has one bidirectional data line, the protocol defines what side is to drive the line while the other listens. Not somthing that would be easy to do with normal line drivers.

At any rate, 6 pin MCU's would be cheaper and smaller.

DaveC

Reply to
DaveC

Well, in my case, I also wanted traffic control. Basically make subnets of I2C devices with the same physical address individually addressable from the master side. I also wanted to do it with as small PCB realestate as possible. The phillips device could be nice if you don't need that additional functionality and I indeed thought about that but I couldn't find a distributor who sells small quantities (well I might not have searched hard enough). I went for an 8-pin AVR MCU.

Regards, Andras Tantos

Reply to
Andras Tantos

Andras,

If I want to support clock-stretching from the slave-side what will be the way? If I want to go as high as 400kHz then what? Its of course depends on the micro. speed so what speed should I use?

Thanks, Nadav.

Reply to
Nadav

Only

the

To do this, I suppose you supply a signal to the repeater to pass or to isolate. The PCA9515A has a control input to accomplish this.

Meindert

Reply to
Meindert Sprang

The issue of clock stretching on the SCL line is in hardware the same as the ACK-bit processing on the SDA line. Of course, that's different if you look onto the protocol. For 400kHz use a really fast micro! Such as Scenix. Maybe the better way is to use a CPLD or FPGA and do it in hardware.

regards - Henry

Reply to
Henry Kiefer

Nope. I'm using a version of soft-addressing with GUID-s and I2C bus-arbitration to individually address my 'switches'. Something similar to what the 24LCS61 does.

Regards, Andras Tantos

Reply to
Andras Tantos

The problem I had was that you would need bi-directional drive on the clock line as well. You can't do that with digital logic (or SW operating on digital values) without introducing spurious edges on the wires. That's fine for the data lines as long as they happen when the clock is incative, but not acceptable for the clock line.

So, in order for this to work, you'd need:

- Analog electronics

- A/D converter (and quite fast ones)

Since the code on a 8MHz AVR was able to go as high as about 50kHz, I would say you need something far more powerful than that. Yes, a CPLD is probably a good solution.

Regards, Andras Tantos

Reply to
Andras Tantos

fine

sure.

good!

strange idea but maybe it works!

If you have any form of programmable logic device already on the board, that is the best solution! Unfortunately, I only have practical designs made in the area of bit-banging as master and designing large i2c-busses across several systems (several meters with say 30 slaves).

Use Ethernet... and low-cost Ethernet switches *lol

- Henry

Reply to
Henry Kiefer

OK. but lets say I only need the simple case in which the clock goes from the master to slave only. One direction only. Then my problem is the data line only. And the same spurios edges problem. I thought if I'll buffer one bit and at the 8th bit I'll stretch the SCL to the master and wait untill the slave acknowledge and only then acknowledge to the master. Should it work? What will be the penalty on performance?

Regarding the frequency issue, what will be the minimum samples in eack clock duty cycle? What is 8MHz AVR?

Thanks again!

Reply to
Nadav

You basically have two ways to go:

- Understand all the protocol details and know when to switch the direction in the data-line. In that case you won't introduce any glitches on the data-line but any non-standard communication would brake your implementation. This is the case when you have to introduce some buffering, and yes, you would have to use clock-streching on the ack bit.

- Go the dumb mirroring way and accept the spurios edges on the data lines. Since direction change is done by monitoring the data and clock lines, ACK bit transmission happens automatically as well and you don't have to use clock-streching.

Well, I didn't do that exhaustive mesurements. But I run a couple of test runs in the simulator counting the clock-cycles it took for the CPU to process each phase of its statemachine and that seemed to be a reasonable speed. I might be off by a couple of percentages but not by an order of magnitude.

AVR is an 8-bit micro form Atmel. 8MHz is it's clock-rate.

Regards, Andras Tantos

Reply to
Andras Tantos

I've made my code and documentation available here:

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Regards, Andras Tantos

Reply to
Andras Tantos

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