Fujitsu MB90440G CAN question

"Geoffrey Mortimer" schrieb

I do not understand your question?!? Physically, a 16 MHz clock is sufficient for generating 1 MHz CAN-frequency just use an appropriate Baudrate prescaler. Maybe you are concerned if the CPU can handle the interrupt load, i.e. non-CAN-function of this uC.

Regards, Taso

Taso, thanks for the reply.

It is the CAN module which concerns me. If there are three independant CAN modules, these should then all be able to work simultaneously at 1Mbps. If, on the other hand, the three CAN channels are somehow implemented in a single hardware module which uses, for instance, polling (as with the Infineon TwinCAN), there may be a limit to the traffic which can be handled simultaneously on all channels.

Since the processor is going to be configured as a dedicated CAN peripheral, the 20 8-byte packets per millisecond it will need to handle should not be a big problem.

For bit sampling, any clock down to 8MHz will work fine.

Regards Geoff

in theory it can, the problem is what are you going to do with the data. Have you checked that you can get these chips? The fab plant was hit by an earthquake last june as far as i know they still havent got it running yet.

Have

yet.

The data are to be written to a 71V30 dual port RAM feeding an MC8245 processor. The DPR and uC together form a compact, intelligent 3 channel CAN

• DUART peripheral.

Interesting news about the fab!

Au contraire --- I think they will. 1 Mbit/s CAN bus sending 8-byte CAN packets --> ~ 130 bits/frame (assuming 2.0B, i.e. 29-bit identifiers) gives you around 7700 frames/ssec. That's roughly 23 messages per millisecond, per CAN port.

So you're talking about roughly 85% bus occupation there --- unless you manage to keep operations on all three busses almost perfectly synchronized, I strongly doubt you'll manage to reach that kind of throughput. You have essentially no headroom left to manoeuver.

Au contraire --- I think they will. 1 Mbit/s CAN bus sending 8-byte CAN packets --> ~ 130 bits/frame (assuming 2.0B, i.e. 29-bit identifiers) gives you around 7700 frames/ssec. That's roughly 23 messages per millisecond for the three CAN ports combined.

So you're talking about roughly 85% bus occupation there --- unless you manage to keep operations on all three busses almost perfectly synchronized, I strongly doubt you'll manage to reach that kind of throughput. You have essentially no headroom left to manoeuver.

"Geoffrey Mortimer" schrieb im

OK, understood. As Hans-Bernhard said, the busload is very high. At 16 MHz the shortest timestep is 62,5 ns. How fast can you poll the registers?

As Hans-Bernhard said it is very difficult at these busloads! Every ~ 43 µs a CAN-message arrives in the buffer, so you will need a very fast main-loop for polling them. I think that you'll need a CPU which is driven with +50MHz.

Complied.