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Debugging problem on a LPC2103 with uLink

Hello. I've a problem with LPC2103. I've two boards. The first-one is a Silica Demo Board with a Philips (with Philips logo) LPC2103. The second one is a home built board with only a NXP (note not Philps marked!) LPC2103 and just supplies and xtal.

I've a Keil uLink and I use uVision3 for Arm. So, I can program both MCUs and everything works well. Unfortunately I can debug just only the Silica demo boards, on my home built board doesn't work. If I put the MCU in run mode the program doesn't go; if I put a breakpoint the program doesn't stop. With Silica board I can do all of these operations.

I checked the layout and all board connections are correct respect to the schematic of jtag connector of uLink (got on Keil web site).

I sniffed all JTAG net and I didn't see any suspectous signal. No noise.

I pushed the power supply of core to 2.0V on my board like Silica board after reading an errata from NXP regarding a bonding dropout voltage....nothing appened.

May be a problem because I'm using an NXP marked MCU instead of a Phlips marked MCU? I didn't find any note regarding mask errata or similiar (silicon problem).

Can anyone help me?

Best Regards

Ste

--

Ogni problema complicato ha una soluzione semplice...per lo piu` sbagliata
[cit. Franco, i.h.e. 20.01.2007]
Reply to
PeSte
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I'm kinda new to this, but here goes. Clock speeds? The JTAG must communicate at no more than 1/6 of the system clock. Is DBGE set right? I believe that this must be low when the chip comes out of reset (but I'm not sure on the specifics) or JTAG will not be enabled.

Reply to
Anthony Fremont

Hi,

I have a cpu board with the LPC2104 and I just checked the schematics. I recall the following issues:

- No pull-down on RTCK for debug purpose

- Jumper on dbgsel to VDD

Reply to
<->

- wrote: [...]

Hi, on my own board there is dbgsel on VDD, too. This apply with datasheet.

I'll try removing the pull-down on RTCK, thanks

Regards Ste

--

Ogni problema complicato ha una soluzione semplice...per lo piu` sbagliata
[cit. Franco, i.h.e. 20.01.2007]
Reply to
PeSte

Anthony Fremont wrote: [...]

Hi, have you some document about this?

On the Silica demoboard there's a 14MHz xtal (debugger run) On my own board there's a 13.5MHz xtal (debugger doesn't run)

I always uses JTAG speed over 1/6 of system clock. I tried all JTAG speed from 100kHz to 1MHz but nothing changed.

the pin is DBGSEL and must tied to VDD to go in debug mode. The pin works properly because if I don't set it correctly I can't download the software via jtag.

Regards Ste

--

Ogni problema complicato ha una soluzione semplice...per lo piu` sbagliata
[cit. Franco, i.h.e. 20.01.2007]
Reply to
PeSte

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