Boot Sequence for Sharp Micro Controller LH754xx (LH75411, LH75410, LH75401, LH75400)

I assume the Sharp "bluestreak library" supports these chips? (I use the LH79520). It's a useful resource for getting things up and running, pinching initialisation sequences, register names etc.

Hi,

yes, this is right. Actually I am trying to use the startup sequence given in the library. Nevertheless, I am facing some problems. I compiled the kev..._startup.asm and linked it to my C programme. The assembly source shows this:

Disassembly of section .text:

0000001c ea000001 b 00000028

00000024 e1a0f000 mov pc, r0

0000004c e1a0f000 mov pc, r0

I am loading this into the internal SRAM via JTAG and step through it. Since my FlashRam is not working yet, I have to start the programme at address 0x0 manually (BTW: which processor mode should I use?). As you see in the code, from adress 0x0 it jumps to 0x20 which holds the instruction "ldr r0, [pc, #232]". Actually, this instruction fails! The JTAG programme (OCD Debugger) says: "Processor running" and if I halt the device, the cpu shows an undefined state (Processor mode is

How this? Did I forget something? Stack settings probably? But all this should be handled by the startup sequence!

Any help is appreciated!

Daniel

Sounds more like a problem with the debugger to me. My code starts like this (remember it's for the LH79520 though!):

-----------------------------------

.equ MODE_USR ,0x10 .equ Mode_FIQ ,0x11 .equ Mode_IRQ ,0x12 .equ Mode_SVC ,0x13 .equ Mode_ABT ,0x17 .equ Mode_UNDEF ,0x1B .equ Mode_SYS ,0x1F /* only available on ARM Arch. v4 */ .equ I_Bit ,0x80 .equ F_Bit ,0x40

/* Locations of our memory system */ .equ MEMORY_Limit ,0x60008000 .equ RuntimeStackTop ,0+__ram_size /* svc mode stack (our main runtime stack)

_runtime: _reset: b init_stacks _undefined: b _undefined _swi: b osSWIint _prefetch_abort: b _prefetch_abort _data_abort: b _data_abort nop /* reserved location */ _irq: /* take vectored interrupt */ ldr pc,[pc,#-0xff0] _fiq: b _fiq_handler init_stacks: /* --- Initialize stack pointer registers */ /* Enter IRQ mode and set up the IRQ stack pointer */ MOV r0, #Mode_IRQ orr r0,r0,#I_Bit orr r0,r0,#F_Bit /* No interrupts */ MSR cpsr_c, r0 LDR sp, =IRQ_Stack

/* Enter FIQ mode and set up the FIQ stack pointer */ MOV r0, #Mode_FIQ orr r0,r0,#I_Bit orr r0,r0,#F_Bit /* No interrupts */ MSR cpsr_c, r0 LDR sp, =FIQ_Stack

/* Enter ABT mode and set up the ABT stack pointer */ MOV r0, #Mode_ABT orr r0,r0,#I_Bit orr r0,r0,#F_Bit /* No interrupts */ MSR cpsr_c, r0 LDR sp, =ABT_Stack

/* Enter IRQ mode and set up the IRQ stack pointer */ MOV r0, #Mode_UNDEF orr r0,r0,#I_Bit orr r0,r0,#F_Bit /* No interrupts */ MSR cpsr_c, r0 LDR sp, =UNDEF_Stack

/* Set up the SVC stack pointer last and return to SVC mode */ MOV r0, #Mode_SVC orr r0,r0,#I_Bit orr r0,r0,#F_Bit /* No interrupts */ MSR cpsr_c, r0 LDR sp, =SVC_Stack

John,

thanks! I will try your stack setup. I am still supsecting the stack...

stack) */