Application processor with fast parallel I/O

DDR data rate is sort of misleading. The data are clocked in/out at this rate allright, but the processors I have seen do one cacheline at a time (32 bytes) and add to that quite a number of initiation cycles. Perhaps the largest ones do take advantage of open pages etc. but the smaller one are unlikely to do it - which in practice yields around half the clocked data rate.

Dimiter

Well if you can retreat somewhat on the "hundreds of MB/s" the MPC5200B can be quite useful (and I could probably offer more help about it than the manufacturer meanwhile :). It can do 2 cycles per 32 bit at 66 MHz (132 MB/s) on a generic bus, and it can do 66 MHz PCI (32 bit). However, while 66 MHz PCI is 1 longword per clock, it will burst only a cacheline at a time (32 bytes, 8 beats). Not sure how many burst initiation cycles this was taking.

Dimiter

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Thanks, that's /very/ interesting. That makes life an awful lot simpler. I'm less familiar with the Zynq than with the Altera SoC FPGAs, but I'll have a dig.

Theo

The one that I used, a long time ago, had a hugely programmable SDRAM interface. I can't remember the chip, but it was a Motorola with a PowerPC, which should date it. That SDRAM interface could have been programmed to make life easy on the FPGA, I think.

But -- I can't talk to this TI part; I just skimmed the data sheet.

Could it have been the 8240 or 8241 (same pinout, same part really, newer version). I have used it - it has a 64 bit wide SDRAM interface and it is hugely programmable, but it does burst one cacheline at a time all right, which is the speed killer I was talking about. I am not sure if one could stop the refresh completely, its period and other related stuff are programmable of course but I don't remember (may be never looked for it).

Dimiter

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picoZed also has Vcco for two banks on the connector also. For the Z7030 picoZed these are banks 34 and 35.

Thanks. I've now found a few Altera SOMs that also expose the Vccio pins, which makes life a lot easier. Can't remember which offhand, but Altera provide a handy list of all of them:

Thanks for the other discussion in this thread. It helped me refine that what I wanted was an SOM - which may expose Vccio - rather than a dev board which typically don't. As it turns out the SOM form factor is also more amenable to my application. Being able to stick to the SoC FPGAs solves a lot of problems and means not having to pretend to be a random memory interface just to get data in and out.

Theo