Hi, I have a novel application that would benefit from an analog "fifo" type of memory, much like the digital fifo.. I have to store a small number of analog signals in a queue before they can be converted to digital via an ADC.. does anyone know of such a chip ? I need at most, 32 analog "memories".. the input rate could be as high as 1 MHZ, but for very short bursts.. the output rate will be in the order of 200KHZ or so. I also require 12 bit accuracy and an FSD of 3 Volts max. TIA
Bucket-Brigade devices and the Winbond/ISD chips came to mind as I read the OP, but not only do they not meet the specs, digikey shows all their Panasonic BBD's as obsolete.
You can use four CMOS 1-of-8 analog switches (standard CMOS part
4051) controlled by appropriate clocking logic, each 'output' connected to an appropriate value capacitor. This would have to be 'read out' fairly quickly after the sampling, before the capacitors discharge.
What is this needed for? Aren't 12-bit 1MSPS A/D's readily available?
You are looking for a switched capacitor array. You can find some theory online, look for example for the article "A Multi-GHz, Multi-Channel Transient Waveform Digitization Integrated Circuit" or this one:
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In these days, however, I think that the "digital" way is better and cheaper. With some high-speed ADC and one FPGA, you can acquire analog signals at several GHz without having to mess with custom chip design, programmed propagation delays and so on.
Thanks for the input.. however I did omit one thing.. LOW power... I know there are fast ADC's to do this job, and I am experienced with megasample systems, but I was looking for an alternative solution so I could used a low power micro such as the msp430.. i have a severe power budget to contend with that I am unable to meet with a more conventional approach..
Then perhaps my CMOS analog-switch idea is just the thing. Looks like digikey has 74hc4067's (16 to 1 analog MUXes), and they're cheap enough in quantity, so buy two for each unit. :) Use a 4066-type switch to connect the switch array to the input which you sample at
1MSPS, then switch it out and then (using another 1/4 4066) switch in your A/D (if its input impedance is too low you'll need another buffer here, in addition to the one described below), to which you 'play back' the values at 200kSPS. There's some "design considerations" on the analog side of this thing. If what you're reading doesn't have a low enough output impedance, you'll need an op-amp buffer between it and this switched-capacitor idea, and the op-amp will have to provide enough current to charge each cap to the current signal's level, which may exceed your power budget. The capacitors obviously need to be scaled to be large enough to hold to 12-bit accuracy between sampling and being read back (worst case, 200kSPS @ 16 samples = 80 microseconds), but not so large as to create an unnecesarry load to the buffer. I don't know of a single chip to do this sort of thing, but you might ask with a careful crosspost to sci.electronics.design and sci.electronics.components, where other knowledgable people who don't read here may have some good ideas.
Not all that novel ... the Tektronix 7D20 plug-in (designed over 20 years ago) has two of these (CCD shift registers) in its front end for exactly that purpose. But those are custom Tektronix chips, now obsolete and not generally available.
But low-power, 12-bit, 1 Msps ADCs are readily available these days -- for example, the AD7450 from Analog Devices is rated at 1.3 mW max and operates at 3 or 5 V. $4.00 in quantity.
Another approach to consider may be to use either multiple ADCs and/or multiple sample/hold circuits. Also, you might consider using a fast ADC that can be rapidly switched in and out of low-power mode, so you can wake up, do a burst of conversions and go back to sleep to save power.
12 bits means 1 / 4000 in relative accuracy - a stiff spec for any analog processing. For 3 V full scale this turns to an accuracy better than one millivolt.
IMHO, there is no cost-efficient way to implement it with an analog sample-hold compared to a fast enough A/D on each line separately and storing the digital data.
Yes, but there are ways of compensating for droop. If two of those inputs are committed to a reference and 0V, and *if* the capacitors are close tolerance, and *if* the impedances are matched, it *might* be good enough...
the real issue is whether the 12bits need to be accurate or merely present. In order to sample at 1MSPS with 12 bit accuracy, the front end needs to settle to within 0.02% in a couple hundred nanoseconds . Also in order to have the noise level lower than 1LSB , given the large noise bandwidth, input and load impedances need to be very low . Can you say good bye, low power ?
12 bits at 1MSPS is what some digital cameras do , and in order to reduce noise they employ a technique called correlated double sampling .
How severe ? - numbers always help.... If you are unable to find a CCD or similar true analog scheme, then you could look at low power ADC-DAC combination, controlled not by a uC, but by a CPLD. uC are spec'd in hundreds of uA/Mhz, whilst CPLDs can be ~34uA/MHz. You will have some latency in the ADC and DAC already, and more can be added in the CPLD, if you need a lot more, a small ram can be used as an analog FIFO.
Which is not very fast by modern terms. This does not really differ from the requirements set by any analog memories. At this point the problem is sampling, i.e. it is an analog problem.
I don't think so. We are using ADCS7476 (12 bits, 1 Ms/s, < 1 mA @ 3V, SOT23-6, $2). Cheap chip but still seems to fulfill the promises given in its datasheet. That or an equivalent ADC coupled with a low-power CPLD (e.g. Lattice 4000ZC-series) should give you over ten samples of buffer memory (at 256 cells) without adding too much power consumption.
If more memory is needed, a low-power DSP run at a low frequency could also be possible, and then the results can be handled right away.
One of the nice features in modern SAR-ADCs is that many of them are track-and-hold instead of sample-and-hold. This gives much more sampling time. For the converter mentioned above, the tracking time is over 300 ns, and the input capacitance is around 30 pF. In order to get a 12-bit settling, around 9 time constants are required, so the time constant has to be around 30 ns. I.e. the driving impedance has to be a kilo-ohm or less. Not a very difficult requirement to meet.
Correlated double sampling is a good idea when you can use a reference which is sampled with the signal itself. In a CCD the element may give the dark level signal between pixels. CDS removes bias errors in the amplifier chain. However, CDS multiplies the sampling noise by sqrt(2), as two samples are required.
In the previous answer I didn't notice the "1 MHz" specification, I was thinking about frequencies much higher! :)
I can't answer to your question, unless you specify with numbers what you mean with "low power". If we aren't speaking of few mW, IMHO the best choice is to find a low-power microcontroller with 1-MHz ADC integrated (for example TMS320F24xx, but I think they are on the range of 20-200 mW).
This is a simple solution. However, the ADC specs have to be read carefully. Most ADCs integrated into MCUs are not as good as their external counterparts. OTOH, an external converter costs only a few bucks, so if the MCU supports microwire or whatever protocol the converter uses, using an external one is not a big problem..
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