A question about SDRAM's refresh!

Aug 22, 2005 3 Replies

Hi! I am writing a SDRAM controller with VHDL.And I have blocks of data t store into the SDRAM very quickly,so SDRAM should be in BURST writ state,isn't it?My question is if the BURST write state continues a lon time(such as 1 second),should I stop BURST write and perform an AUT REFRESH operation per 64ms(because SDRAM should be refreshed per 64ms)?I other words,if I do a BURST write,can I omission the AUTO REFRES operation?



Thank you for your help!


This message was sent using the comp.arch.embedded web interface o

formatting link


Probably not. The other rows would probably discharge without refresh.

Also, check that there is no upper limit on the row-select time - 1 second is an awfully long time.... I know there used to be maximum tRAS specs on old-style DRAMS, I think for power dissipation reasons. Looking at a Micron datasheet I have to hand, they show a maximum ACTIVE to PRECHARGE time of 120uS, so a 1 seond burst would be well in excess of this.

Why would you want to burst-write for 1 second anyway - you can only write within that row so there's a limit to how much data you can store...!

To follow on Mike's comment, I think you'll find the burst has a max length. 4096 IIRC from Micron's sheet. You can activate refresh between bursts.

If you're writing for a full second, there's got to be a lot of dead time in there, and you should be splitting up the bursts and enabling refresh in between writes.

And you didn't mention - SDR or DDR? What chip are you using for reference?

Richard

If the device has concurrent precharge then you should be able write continuously as long as you write say in bursts of 4 or 8 in sequentially different rows or banks with auto-precharge. Normally it's a matter of mapping the "incremental address" of your counter to row, column and bank addresses.

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required