16-bit SPI trying to read from 22-clock cycle ADC

Bill · 2009-09-08T13:53:43+00:00

Hi,I'm trying to pull out data from the ADS8320 (a 16-bit ADC by AnalogDevices. See bottom of page 10 in ) using the SPI in anAT91SAM7S256. The problem is that the ADC needs 6 extra clock cyclesto sample the analog signal, before the 16 cycles that will outputeach of the conversion result bits. So, a complete ADC cycle involvesa minimum of 22 clock cycles. Now, the SPI in the AT91SAM7 (and, asfar as I've seen, in all other MCUs), cannot generate more than 16clock cycles within one CS activation.How am I supposed to do this, in an elegant way? Of course I could bitbang those lines, but I hate doing that, because it adds load to theCPU, and doesn't take advantage of the SPI and DMA.The AT91SAM7S256 allows holding the CS low until a new device isaddressed, so I could initiate two 11-bit readings in a row (in such away that the ADC would think it is a single CS assertion with 22 clockcycles inside), and discard the bits with no information, but that'sstill ugly to me. It would use the SPI, but not the DMA, and the tworeadings would be different (the first one should hold CS low. Thesecond one should leave it high), which is kind of non-homogeneous.Any more elegant ideas?Thank you.

Sep 08, 2009 40 Replies

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lowcost 16 years ago

Ulf Samuelsson ha scritto:

2=E7: using spi_out (mosi) for CS/SHDN and trasmitting the right pattern, coded n times in flash table, while receving Dout on miso.

a small RC delay on mosi will insure that CS fall after DCLOCK low, according with tCSD.

a small RC delay on miso will insure that valid Dout will be sampled on DCLOCK falling, according with thDO.

all this running under DMA_PDC , sampling n samples block in n lenght ram buffer.

regards

--=20 lowcost

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16-bit SPI trying to read from 22-clock cycle ADC

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