Re: Are chips more vulnerable to witchcraft than transisters?

Paul · 2026-06-19T20:00:29+00:00

They're generally scale-invariant.The scribbling on them is smaller, but then we put more of thescribbling, so they end up having the same X-Y dimensions for the price.If the dimensions X-Y were to be made too small, it would makethe devices too hard to cool. It helps to make them a "decent size"in the X-Y, so the heat sink works for us.You cannot make them too much thinner or they would snap frommechanical stresses.The chips convert electricity into heat, and as a side effect,they do your taxes. And yes, they are pretty amazing.At one time, the scribbling was so large inside, a guy with agraphite pencil at the fab, added some missing connections toa chip, by using his pencil to leave conductive marks on thechip, causing the chip to work. The guy who did it, was onmy soccer team :-) The chip in that case, the "lid" was heldon with cello tape on one edge, and you could flip the lid upand look inside for the pencil marks. And the chip, it then worked.The chip was not very complex, but I think the developer waspretty proud of being the first one of its type, at our fab.It's possible there wasn't any "simulation" done for that chip,and that's why the missing traces were not noticed. We didn'teven have a design review for that chip -- if we had reviewed it,I have a suspicion we would have caught that mistake.Today, the scribblings inside are quite small, even for amicroscope to look at. At one analysis place, they use anelectron microscope, to examine the scribblings and reverseengineer things (check for patent violations).It's long hours of work to make them. It would take too longto design them, if it weren't for the repetitive natureof some of the structures (you just make xerox copies ofsome of the items and lay them down side by side). The RAMchips in your computer are like that. Very uniform patterns.When the things they do, are closer to being softwaresubroutines (adhoc state machines and so on), it's a loteasier to make mistakes. One chip had 4096 registers inthe...

Jun 19, 2026 Last reply: 3 months ago 21 Replies

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Radiation-Induced Transients & Single Event Effects (SEE)

The Physics: Space is flooded with heavy ions and high-energy protons. When a cosmic ray passes through a semiconductor, it leaves a track of electron-hole pairs (charge ionization).

The Space Constraint: Because nano-wide wires have such incredibly small parasitic capacitance (\(C\)), it takes a vanishingly small amount of deposited charge (\(Q\)) to cause a massive voltage spike (\(\Delta V = \Delta Q / C\)). A single cosmic ray striking a nanometer-scale node can easily flip a bit (Single Event Upset) or trigger a catastrophic short (Single Event Latchup).

How Aerospace Engineers are Adapting

To survive these constraints, space-grade chip designers are moving away from traditional copper interconnects:

Barrierless Ruthenium (Ru) and Intermetallics: Many advanced space ICs are exploring replacing copper with alternative metals like Ruthenium or compounds like \(CuAl_{2}\). Ruthenium has a much shorter electron mean free path and stronger atomic bonds, meaning it doesn't suffer from high-frequency resistivity scaling or electromigration nearly as badly as copper when shrunken to the nanoscale.

Redundant Mesh Networks: Implementing AI-driven EDA tools to automatically design heavily redundant on-chip power and signal routing so that if a few nanometer traces succumb to electromigration, backup paths keep the chip alive.