Hello All,
I am in need of your experience in clarifying a question that is confusing me a lot. I have done my research and studied information from various text books and stuff.
I am designing a Schmitt trigger (CMOS) and this design follows the basic design in Digital Integrated Circuits (RABAEY) - Pg 367 (my book). I will draw an ASCII art if anyone wants to look at it.. However, firstly I used ABN 1.5u process to simulate the circuit using PSPICE. The switching threshold voltages Vm+ and Vm- follow my hand calculations. The W/L of the inverters were 13/2 for PMOS and 6/2 for NMOS. The W/L of the feedback transistors also came out to be the same.
I migrated to new feature size and calculated the Vm+ and Vm- value. Becuase the Kp/Kn ratio is same, I found out that W/L values can still stay the same. For the assigned W/L value, I hand calculated the Vm+ and Vm- value, and it comes out to be the what I want (2 V and -2 V). But, PSPICE simulation gives me a big error.
To achieve the Vm+ and Vm- values of 2 and -2 respectively, keeping the transistors of the inverter configuration same as of previous config (13/2 and 6/2), my calculated W/L ratios for the feedback transistors do not work. I played around until I got the required hysterisis.
Am I doing anything stupid? I have tried my best to pose the question as clearly as possible.
Is there anything specific I have to consider when comparing my hand calculations with PSPICE simulations? (for 0.5u tech).
Any help would be greatly appreciated.
Thanks a lot, Saran