ADC problem with PIC 18LF2525

I'm trying to set up a simple testbed program to read three analog voltages on A0, A1, and A2 (pins 2, 3, and 4, resp.) of a PIC 18LF2525. The Vdd is

+5.0VDC. The ADC is set for 16 bit operation. The ADC clock is set for internal operation. The program sets a channel, waits for 20us for conversion to complete, reads the value, and scales it based on a 5V full scale. When all three channels are read and scaled, the program outputs a message to the RS232 port connected to a HyperTerminal session. The message is sent every 10 seconds.

I tried pulling each input to ground through 100K resistors to get a 0.000V reading but I saw significant voltage fluxuations (over 0.1V) on each channel. I tied a 0.1uF capacitor across each resistor and that seemed to improve the readings on channels 0 and 1 (they stayed pretty consistently at

0.000V) but did not eliminate it on channel 2. It did reduce it, though, to about 0.014V - 0.019V. In looking at the Vdd line with a scope, I saw a significant dip (~100mV) in the Vdd voltage during the message output every 10 seconds. I tried setting up an external Vref+ on pin 5 with a dedicated +5.0VDC regulator and a 10uF and 0.1uF cap to ground. The Vref+ line looked very stable on the scope and channels 0 and 1 stayed consistently at 0.000V but channel 2 is still varying (0.014V to 0.019V).

By the way, I've tried setting the delay time (after setting the channel before reading the value) to up to 1ms with the same results.

Has anyone else experienced this sort of behaviour? Is there a solution for it?

I'd really appreciate any thoughts or similar experiences (or better yet examples) of how this problem can be solved.

Thanks.

Dave

Reply to
Dave
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Hi Dave, I dont know that processor nor the ADC but I have seen a similar problem using an Infineon 16bit C167 processor. Infineon recommend a series connection of a resistor and a capacitor from the channel-line to common/GND. I dont remember the values, but an application note from them will reveal the secret. The problem rises because the ADC is a type using a ladder of capacitors in stead of (normally/old days) resistors. Good hunting. regards Klaus

Dave skrev:

Reply to
Klaus C Nielsen (DK)

I would say that you are probably having a problem with the 100K resistor being 4 (or so)times higher than the input impedance of the ADC. I may be wrong for this particular PIC, but I thought most of the PIC ADCs were in the 25K range. Try dropping that to 20K or so and see if that clears up some of it and make sure the PIC has some good decoupling caps near the power pins.

Reply to
James Beck

Thanks for your suggestion.

I checked the analog section of the data sheet and it states less than 2.5K. I changed the values down to about 2.2K after a voltage follower stage, added a 0.1uF cap across each resistor, put 0.1uF decoupling caps next to the voltage regulators and power pins of the devices, and checked again. It is substantially better now but still has minor fluxuations (+/- 1 or 2 bits), which I can live with. The voltage follower lets me use a fairly high impedance load for my analog sources (to not load them down too much) while still providing a low enough output impedance where 2.2K doesn't swamp it out. I just used a LM324 as the votlage follower.

I separated the analog and digital ground systems and common point tied them at the voltage regulators. That also seemed to help. Part of the problem is I'm doing this on a solderless breadboard so there's a lot of intrinsic noise around.

Thanks again for your suggestions.

Dave

Reply to
Dave

With a MCU integrated ADC +/- 1 or 2 bits is pretty darn good (and usually well within the specs on the datasheet). If you want to get the best possible accuracy from the ADC you usually need to get a good external Vref and use that.

Reply to
James Beck

James Beck wrote in news: snipped-for-privacy@newsgroups.bellsouth.net:

A fine point. While it seems like the OP is generally satisfied with this performance, I'll take the opportunity to point out that there's something very wrong with the tolerance of a design if those 1-2 LSB's were critical.

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Scott
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Reply to
Scott Seidman

"Dave" wrote

Tying the two grounds together at one point is correct, but I would prefer to do it by the ADC (and of cause only there)

Klaus

Reply to
Klaus C Nielsen (DK)

The ADC is in the PIC.

Reply to
Dave

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