CD4046 Question

Find some other data sheet?

Some of them are more informative than others. I don't know who still makes 'em, but I'd look to TI, ON Semiconductor, and Fairchild to start.

The 74HC4046 is very similar (it has one more phase comparator, IIRC, and may delete some other function) -- if you can't find what you want in a 4046 data sheet a 74HC4046, or other 74xx4046 data sheet, may help.

The Texas Instruments data sheet at

Chris (another one)

hmm, you will need also a loop-filter, so it is better to study the data sheet until you understand what you are doing. ciao Ban

Got it 1MOhm, and .002uF ~400Hz I didn't notice the table.

Thanks, Chris

Yes, I need to figure out the values for that too.

Thanks, Chris

The 4046 has as phase detectors a conventional edge-matching PFD plus an XOR (posing as a four quadrant multiplier ;-) ...Jim Thompson

Either the 74HC4046 or the 74HC7046 adds an RS flip-flop phase detector, and (I think) deletes a voltage regulator or something.

At any rate, one of the 'obscure' bits of the CD4046 is deleted, and a somewhat obscure phase detector is tacked on.

A PFD can be made from nine gates (ala Treadway/Thompson) or by using a dual-D plus four 2-in-NAND's ...Jim Thompson

Hi Tim,

Right ;-)

Right "very similar" expect the VCO. They need other values.

CD4046 is much slower then 74HC4046. Earlier days I found only graphs in datasheets that leads me to useful values.

Marte

Just looked up a data sheet. The "extra" D-flop is theoretically a "lock detector"... known by the State of Thompson to be a fraud ;-) ...Jim Thompson

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=A0 =A0 =A0 ...Jim Thompson

=A0 =A0...Jim Thompson

=A0 =A0 ...Jim Thompson

=A0 =A0| =A0 =A0mens =A0 =A0 |

=A0 | =A0 =A0 et =A0 =A0 =A0|

=A0|

=A0 =A0 =A0 |

What would be a good way to indicate lock? I would like to have an LED indicating a lock condition.

Also, I was thinking of using a 555 to shut the PLL off when there is no input signal present. This is needed for my application. I would have the 555 hold for 1 period of the input frequency. If no signal is detected in that time frame, I would have the INHIBIT go to logic 1 and shut off the loop.

Thanks, Chris

well, the lock detector will need some '123 retriggerable Monoflop or similar, a 555 is here not so good. And this works only with phase detector2. Get the datasheet of the 74HC7046, it has a lock detector but needs still the 74123 to get a static output signal. With the PD2 your frequency goes 30% below the lock range without input signal. So the hold time must be longer than that. If you shut off the pll how do you detect anything on the input?

ciao Ban

A method of lock detection for PLL's that actually reach a zero-phase-error lock has eluded designers since I was a kid :-) ...Jim Thompson

With phase-frequency detectors it's pretty easy--the output goes to the rail when it's out of lock, so a window comparator works well.

The 4046 also has the "phase pulses" output that (very roughly) tells you what the phase error is, so you can filter that and use a comparator. I don't think that works as well as the window comparator method.

With an XOR gate or diode mixer PD, you need a second PD plus a 90 degree phase shift. One excellent method is to use a divide-by-4 Johnson counter (aka walking ring). Run the main PD off one output and the lock detector off the other.

Cheers

Phil Hobbs

What output is that?

Measuring something that is exactly zero width is a wee bit tricky.

What you mean is a "close-to-lock" detector is "easy" ?:-) ...Jim Thompson

I've heard anecdotal evidence from several different designers saying that the 74HC4046 doesn't work as a 4046 replacement in their designs, suffering stability issues they found hard to diagnose.

Comments anyone?

I know they copied Treadway's and my designs, but don't know what they bunged up :-( ...Jim Thompson

Phil Hobbs wrote: snip>

Don't write about something you do not know well Phil, that makes "brutta figura"

everything is wrong, In lock is lets say within +/-30° Phaseangle. The phase comparator2 puts out pulses according to how far apart are the edges of the input freqency and the oszillator frequency. the control voltage of the VCO are these pulses smoothed out by the loop filter. When it is in lock these pulses are short, so you can drive a cap through a resistor and with a Schmitt you can create a threshold switch to indicate this fact. It is only with an absent input, that the oscillator drifts to the lowest frequency. And only if you use phase comparator 2. With PC1 the center frequency is put out with absent input signal. But "not in lock" and absent input are two different conditions.

ciao Ban

The filtered PD output, e.g. at the VCO input. When there's a frequency error, the 4046's output goes between tristate and one logic level, so the integrated output rails and sits there. That's one of the good things about it--I've often used it as a lock detector for PLLs whose main phase detector was a diode bridge. (My fave is the Mini-Circuits MPD-1.)

But you don't need to. You can decide how big a phase variance you're willing to tolerate, and set the threshold accordingly. Thought is required.

No. A PLL is in lock when the frequency error is zero, and the variance of the phase error is bounded. You obviously haven't spent enough time in low SNR situations. ;)

Cheers

Phil Hobbs