Epitaxy (epitaxial) refers to layers grown on top of a wafer after it is polished. The alternative is to create layers by diffusing dopants down through the top surface with heat or by driving dopants ions or atoms into the wafer via high velocities. Planar just means flat. All connections and patterns (except for the bulk wafer connection) are on the top surface.
Hi can someone explain the meaning of "epitaxial planar type "??? Tnx dan
Hello All
By the way
Anyone knows why in some devices, using epitaxial layer is good? Good in what parameters? Kindly advise
Thank you
Jason
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In the diffused process that John described, say you have a silicon N-type wafer and wanted to make a PN junction. A P dopant is deposited in a fairly high concentration of the top of an N type silicon wafer, then the temperature is raised so that the P dopant atoms diffuse into the body of the N silicon. At the end of the diffusion step, you would find that the concentration of the P dopant atoms decrease from the surface toward to bottom of the wafer, but not in a linear way-it follows an error function distribution(erf). The P dopant concentration at the surface of the wafer is usually greater than the wafer background N atoms, so that the surface of the wafer has been converted to P type silicon. As you go deeper and deeper into the Si, the concentration of P dopant atoms gradually decreases until you reach the point at which P=N. This is the PN junction depth. Below this point N>P and you are into N type silicon on the other side of the junction. This makes a diffused diode. With the epitaxial process, the N wafer is heated while a mixture of a silane gas and P dopant gas is passed over the N wafer. Silicon doped with P dopant is deposited on the wafer, producing a P type silicon layer on top of the N wafer. In contrast to the diffused process, the concentration of dopant in the top layer is very nearly constant throughout its depth. Ideally, it produces a "step" junction with no N type carriers. In some cases, the dopant can be left out altogether to produce a carrier free(ideally) top layer, which is called "intrinsic" silicon. This distribution of carriers around a PN junction will have a pronounced effect on the electrical characteristics of a device. Leakage current of a diode, for example. Or junction capacitance-avoided for high frequency devices, exploited for varicaps. "Sic hoc legere scis nimium eruditionis habes." (If you can read this, you're overeducated.)
Tnx for the explanation
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