I have to design a power supply with 600v isolation, 12 outputs are 15v at 10mA per channel.
I was wondering if the typical strategy with this type of construction is to use buried vias.
thank you Bob N9NEO
I have to design a power supply with 600v isolation, 12 outputs are 15v at 10mA per channel.
I was wondering if the typical strategy with this type of construction is to use buried vias.
thank you Bob N9NEO
600 volts isolation between the secondaries? At your power levels, you might be able to use single-turn secondaries. But you are probably talking 27 or so pins on one transformer, unless you use several transformers.
I do a lot of isolated-channel stuff, with individual DC/DC sips or transformers. Sometimes the power is also a clock for a delta-sigma ADC or something.
A single planar transformer would be interesting next time.
Coilcraft makes some very pretty planar transformers, but I don't think they can do that many windings.
They go up to something insane like 350 watts.
-- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers
Sounds like gate drivers... :)
I'd suggest limiting that to maybe 2-4 outputs per core, using more and smaller cores (they can be very small indeed at that power level).
You can dog-leg outside turns to avoid too much layer waste, but if cost is no object and space is critical, buried vias (and lots of layers -- upwards of 16 is easily encountered) will help with that.
UL rated FR-4 should handle that voltage with typical (10 mil?) prepreg layers, so the voltage shouldn't be a problem.
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design
I have looked into similar issue. We got the response that 0.4mm solid insulation (0.4mm prepeg) is needed for reinforced insulation, so unless you olan for very thick PCB 2 outputs is possible
If however you only need functional isolation for a gatedriver, that's another story
Cheers
Klaus
Blind vias are something you try to avoid under most circumstances.
In thick stack-ups, they can be simulated by splitting the stack and introducing a thin-film layer, for a multiple stack, but creepage applies if the layer isn't impregnated.
RL
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