Driver for IGBT? (-ve off and +ve on from CMOS)

(off)

That's good to know. I am looking at using an IR21094 chip. Is it true that it supports that configuration (it seems to be the case to me, but I want to confirm).

I will double check, but I think that I have a 12V with +-5V power supply lying around. If not, I can make one from something, even a dual power supply for starters.

Now, I want to make sure that I understand what you mean.

Question: So, the above should work for a "big drive" (which, I assume, applies to my 200 A system). What you write below is simply another option that applies to "smaller drives".

Is that correct?

OK.

I think that I understand.

Which one would you suggest?

Not very feasible... I was hoping to be able to get away with a much smaller resistor...

Thanks a lot...

i

[.. a bunch of good stuff ..]

Just as a BTW: If you are current sensing by placing a resistance in the emitter leg (current Xformer included), a small capacitance across it, speeds up both the on an off times a bit.

Also: I have used back biasing to speed up the turn off of MOSFETs.

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kensmith@rahul.net   forging knowledge

In article , Ignoramus14838 wrote: [...]

I think you may be thinking about IGBTs wrongly. Think of it as being this circuit:

ASCII ART: Collector pin ------------------+------+-----+----+ ! ! ! ! ! --- --- ! ! ! ---Cr1 Cr2 --- (I1) --- ! ! ! ! --- ! ! ! ! ! !/ e ! ! +-----+--! PNP ! ! ! ! !\\ c Q2 ! Rgg' Lgg' ! !!- d --- ! Gate pin ---+/\\/\\/-)))))--+----+---!! --- ! ! Q1 !!-------+-+-- --- s ! --- ! ! Cg ! -------------------+-- Emittor pine

To turn it on, you have to get a charge through Rgg' and Lgg' onto the Cg so it charges up to enough voltage to bias Q1 on. When it starts to turn on, the gate drive circuit also has to provide the charge for Cr1 and Cr2.

Cr2 is really not linear. Its capacitance increases as the voltage on the "collector" decreases. You can sort of ignore this for your initial thinking but you've got to worry about it in the real circuit.

To turn the thing off, you have to get the charge out of Cg so that the gate voltage on Q1 goes low. To do this you have to pull down on the gate pin. You driver circuit, once again, also has to handle the charging of Cr1 and Cr2.

Once you start turning Q1 off, the capacitors I drew in near Q2 come into play. It is really (I1) that turns off Q2. Once Q1 is turned off, the carriers "trapped" in the base of Q2 slwly get eaten up and the device turns off.

I think it should now be clear haw pulling the gate below ground helps. It increases the current through the Rgg' and thus gets the MOSFET off sooner. It also prevents the Cr2 from turning the Q1 back on when Q2 starts to turn off and the "collector" voltage starts to increase.

There is also an unwanted NPN structure in the IGBT. This can cause trouble if it gets enough forward bias. Hopefully, you are staying way from such conditions.

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kensmith@rahul.net   forging knowledge

Ken, are you talking about a snubber circuit?

Yes, looks like it is necessary in my case.

i

Yes, that makes perfect sense.

Can I accomplish negative biasing of the gates by simply supplying proper voltage to a gate driver chip such as IR21094? Or do I have to mess with more add on electronics, etc?

i

Of course. Chips always fail where they do the most damage. Some kind of law of nature.

Terry, I will answer the rest of your post separately, but I would like to know which semikron gate driver do you recommend. I am fully in agreement with the idea of buying more expensive, but perfectly well designed gate drivers. I mean, $3 or $15, who cares. I paid $9.99 for my TIG welder and $60 for four IGBTs and can splurge a bit on a gate driver.

i

Terry, I am thinking of buying a Semikron 23.

What would you say about it? Seems like it can drive up to 200A IGBT.

i

No, take this example:

!!-- Drain Gate -----------! !!--+----+----- Current limit circuit ! ! / --- \\ --- C small Maybe 1uF R sense / ! \\ GND ! GND

If you have to put an R(sense) in yor circuit anyway, a small capacitor across it speeds things up a bit. When you go to switch off, the capacitor holds the source of the FET slightly positive. The time constant has to be much shorter than the time you want your current limit to respond in.

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kensmith@rahul.net   forging knowledge

[...]

Also the breakdown voltage of a very cold MOSFET is lower.

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kensmith@rahul.net   forging knowledge

A key capability in their module for protecting the IGBTs can be seen in the "Vce monitoring" item, pages 3 and 7. If you were to roll your own, you'd want to include such a feature in your circuit. Their isolation circuitry is no slouch either, see their 75kV/us input-output dv/dt spec.

Note the maximum frequency vs gate-charge plot, figure 15.

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 Thanks,
    - Win

I believe the Vce-monitoring catches much more than dead shorts. Any time the IGBT's Vce is significantly in excess of the normal saturation voltage, for an adjustable time, the IGBT error shutoff will trigger. This occurs for Vce > 5.2V for the SKHI 23/12, with Rce = 18k. The time is also user-set, with the Rce and Cce values. Semikron's point is that if the time is short enough, the full IGBT self-current-limit can be sustained at short circuit without damage. Any current that forces the IGBT out of saturation beyond 5.2V for more than the set time will trigger a fault shutoff for that cycle.

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 Thanks,
    - Win

BTW, Semikron has a nice 269-page power IGBT manual on their website (although it's broken into a million pieces). They discuss the Vce- monitoring scene on page 210, and rules for protecting IGBTs against shorts on page 207. "The following important boundary conditions have to be fulfilled to guarantee safe operation: - the short circuit has to be detected and turned off within 10 µs, - the time between two short circuits has to be at least 1 second, - the IGBT must not be subjected to more than 1000 short circuits during its total operation time."

The technique is not able to function as a universal power-limit detector. E.g., if the IGBT is desaturated, but under 5.2V, it can still quickly exceed its thermal power limit. For example, consider Ignoramus14838's Toshiba MG200Q2YS40 IGBT module, datasheet page 3. With 15V gate drive, the collector current goes offscale at 400A for Vce above 4 volts. The current at Vce = 5V (just below the 5.2V trigger) could be as high as 550A, which would be a power dissipation level of 2750 watts. The transient thermal resistance curves show this power level can be sustained for only about 15-milli-seconds, with a 100C junction-temperature rise. A cautious user could reduce the Vce-fault value, e.g. 4V (400A, 1600W, 0.1s) with Rce = 14k, etc., but the IGBT could still be damaged with exactly the right conditions. But this exact condition (a sustained current of more than say 250A, but less than 400 to 500A) may be rather unusual and hard to create.

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 Thanks,
    - Win

["Followup-To:" header set to sci.electronics.design.] On Tue, 11 Oct 2005 03:09:22 GMT, Ignoramus14838 wrote in Msg.

Those look cool. What do they cost?

robert

a decent short from gate to emitter would do it.

what you are loking at is a combination of things - miller effect mostly. There is a non-linear capacitance between gate and collector, call it Ccg. Whenever the collector voltage changes value (say from Vcesat to Vdc when turning off) the voltage slews at some rate, dV/dt. This causes current to flow thru Ccg, Icg = Ccg*dVce/dt. This current flows into the gate circuit, charging up Cge. If the gate driver is not very low impedance, Icg will happily charge Cge up to Vth, and beyond. when turning the IGBT on, Vce falls so Icg flows out of Cge, discharging it - IOW trying to turn it back off.

This can greatly increase switching time (and hence losses) and, if the gatedrive is bad enough, can make the device "latch" in the on-state, with Vge sitting around Vth - but you need a seriously piss-weak gate driver to do that. It can even over-voltage the gate, poke a hole thru the thin gate oxide layer, and KABOOM, one dead IGBT.

a negative gate bias means the switch-off miller current has to supply more charge to reach Vth - instead of supplying Qg = Vth*Cge, it must supply (Vth + |Vnegative|)*Cge. This allows the use of higher gate impedance circuitry. Its not just the resistance, its the inductance too. bad gate drives have high resistance and high inductance; good gate drives have low resistance and low inductance.

to give you an idea, I've worked on gatedrives for 0.5kW - 2.2kW drives that have about -3V reverse-bias, and -15V for 400kW drives (6 300A fuji IGBTs directly paralleled).

modern IGBT designs have much better packaging - far lower inductance, both Lce and Lge. with some of these IGBTs it is theoretically possible to keep the gate impedance sufficiently low that negative bias isnt necessary. Like I said, IR wrote a pretty good paper on the topic - why you dont, in theory, need -ve bias for little IGBTs.

In practice, if you screw up the gatedriver, your circuit is going to go BANG. If you really know what you are doing, and are very good at taking measurements, its fairly easy to dewsign gatedrivers and make them work. OTOH if you are not too experienced, its very easy to destroy many, many IGBTs.

Generally the gatedrive is a lot cheaper than the IGBTs, so its sensible to throw -ve bias at it. For little IGBTs, it can be as simple as a zener in series with the gate resistor, with a 100nF cap across it.

Cheers Terry

Well, sure, but it protects an expensive drive from complete failure when that short occurs. That's why the semiconductors are often SC rated, because it's an important consideration for the customers.

Turn off conditions from a dead short are particularly demanding, and part of the reason for the negative gate bias.

Best regards, Spehro Pefhany

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"it\'s the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

here's one simple solution: use an optocoupler to drive a FET driver chip, running from a +10V/-5V supply. connect the supply 0V to the IGBT emitter, +10V to the driver chip Vcc and -5V to the driver chip gnd. that way the driver chip "sees" a 15V supply, whereas the IGBT "sees"

+10V and -5V.

we used to use tens of thousands of UC3842 smps chips as gate drivers. An opto drove the 3842, which ran from a 15V isolated supply. the 3842 Vref output was connected to the IGBT emitter, giving +10V/-5V gate drive. We had hefty caps from +10V to 0V to -5V. for little drives. for big drives, we used +/-15V supplies.

for really little drives (< 2kW) we used the series zener trick. get a

15V FET driver, with a 15V supply. bung a 5V zener in series with the output, with a 100nF cap across it. When the gatedrive output is high, 5V is dropped across the zener, charging the cap - the cathode end of the cap is 5V below the anode end, and the gate gets 10V.

when the gatedrive output switches to 0V, the anode end of the cap is at

0V. The cathode end of the cap is 5V more negative than the anode end, so the gate sees -5V. The 100nF cap needs to be at least 10x the gate capacitance. For larger IGBTs, 1uF would be better.

this is probably the easiest option for you, and works with *any* gate driver. Make sure you use a stompy zener though - you dont want its series impedance to be large compared to your gate resistor. Think BZT03 or suchlike.

gatedrives are tricky, and until they work you kill a lot of IGBTs. why not just buy one from Semikron.

yes but no. You would need a seriously low valued resistor (< 10R) to even attempt to hold the IGBT off wrt Cmiller, which would quite successfully bugger up the gatedrive. not to mention the 15V^2/10R = 22W or more power dissipation when the gatedrive is ON.

Cheers Terry

What kind of output stage does it have? How fast does its voltage change to accommodate an instantaneous change in load? Generally there're capacitive and inductive aspects to any large power source's output. A capacitive aspect means the current would be much higher than the "current limit" for a short time after an open circuit (during which the output voltage was at the maximum). If this happens, and lasts too long, an IGBT operating into a short without fault shutoff could be damaged.

An inductive aspect means the voltage will rapidly soar after the load is interrupted, as the inductance tries to enforce no change in the current.

$50 was too much?

Yes, although the switching delay times could mean that the output will be disconnected for a time on each cycle change. This is more tightly controlled in full H-bridge drivers.

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 Thanks,
    - Win

and a buddy of mine who designs smps for space apps uses +/-15V drive because (AIUI) radiation can reduce Vth of a MOSFET, even making it negative. betcha that cost a lot to find out.

Cheers Terry