Input stage mess

add a C across the cable to resonant out the L.?

I don't undestand why your cable looks inductave anyway?

Is the source Z of the generator equal to the characteristic Z of the cable?

The only way for the cable to look inductave is for it to be short length (probably true) and for the generator source Z to be lower then the cable characteristic Z.

Is the cable charateristic Z 50 Ohms? Whats the generator, a low Z mic...is this for audio? Why go to 1 MHz?

Mark

Well, I've finally got doing that low noise preamp: the target is

Lots of interesting pbs to solve. One remaining thing is some stability issue wrt to cable/generator impedance. The input stage will be 4 to 6 paralleled Interfet's IF3602. They'll work at a low servoed 1V VDS to minimze thermal noise problems. Under those bias condition the JFet will show about 300pF Cgs and 180pF Cgd. The Jfet is servo-cascoded so that amounts to and equivalent 480pF Cgs. The closed loop preamplifier show an input impedance that has a painfull negative real part input admittance. Admitting a first order response, the input admittance is:

Cgs w^2 Yin = -------------- with WT = 2 pi GBW and beta= feedback network attenuation WT beta + j w

This translate to an equivalent parallel network:

Now the figures: designing for a 10 loop gain (WT beta) at 1MHz this give a low -12R for the real part at high frequencies and will give a nice oscillation with the input cable impedance (estimated between 300nH & 500nH). As the generator impedance is low, the easy way to deal with this could be a serie RC in parallel with the input (sort of 2-5 nF and under 12R resistor). Unfortunatly a 10R resistor is 410pV/rtHz and 41pA/rtHz which translates to about 130pV/rtHz across the 0.5uH cable inductance at 1MHz. A bit more than I would like. More, this 10R is dangerously close to the -12R value, which didn't accounted for additionnal parasitic poles and will probably be lower. Plus cable resonance with the input capacitance will rise the noise level.

I can't insert a damping resistor in series with the gate connexion for noise reasons (200pV/rtHz is a super low 2.5R noise resistance).

I've thought of a lot of schemes for neutralizing Cgs, but found nothing practical.

I also can't run the input stage open loop, which would solve this issue but will raise some others.

Any idea?

"John Larkin" a écrit dans le message de news: snipped-for-privacy@4ax.com...

at

Cgd.

network

the

be a

resistor).

to

than

level.

but

Here it is.

V V | | +------------------------+--------. | | | | .--+ .--+-----+--------. | | | .-.R3 | .-.R4 | /| | | |\\ | ---| | ---| | >| /-|-' '-|-\\ |< ---| | ---| | |-< | | >-| | '-' | '-' /| \\+|--+--|+/ |\\ '--+ '--+ | \\| | |/ | | | | 2 V | clamp --. | .-------------------' | | | | | | | ___ | | | | | .---------------------|___|-. 10u | J1 |-+ | +-|J2 | | | R2 | || | | | | | | ___ | |\\ | in -+--||--+--->|-+ | +-|-+-out .-. .-. '---+---' | | GND | | GND .-|-/ | | | | | | | V V | | |/ | | | | | | .-----------------------. | | 1M'-' '-'1G | | Precision |--+--||--+ | | V | current mirror | .-. GND | 160mA '-----------------------' | | | to /| | | | 240mA /+|-GND'-' '------------------------------------------+-< | | | \\-|-+---' | \\| | '-||---'

J1 and J2 are 4 to 6 paralleled IF3602, no source degeneration (noise), running at 20mA/transistor. R3 and R4 are one per transistor and 50R (1V across the Jfet, 1V across the R)

The feedback path has _low_ impedance (1 fb path per jfet, 1R/27R).

As you can see, nothing terribly fancy. All lies in the details (like the subject of this post).

For the problem of interest here, it comes from the differential input voltage which rises 6dB/oct with a 90° shift wrt to the input voltage (due to the open loop gain pole) and the JFETs capacitances across the inputs (1.45nF between the preamp in+ and in-) which introduces another 90° shift for the current injected at J1 gate, hence the negative resistance. Exactly the same pb as an emitter follower loaded with a cap.

Why is the input stage differential? Seems to me that doing that increases the noise by 1.41 or something. And all those current sources look complex and potentially noisy to me.

What are you using for the clamp? I have a similar problem... I need a pA leakage clamp that can swallow some 10s of mA overloads.

John

Hmm. Looks like the origin of the problem is the overall feedback. Do you really need the virtual ground? If not, how about making the input stage a feedforward 20-dB stage instead, and adding the feedback amp afterwards?

Since your JFETs will be reasonably linear at that I_D, the feedforward path will have low gain, and hence you can use a higher-noise amp to generate it. This of course will require a bit of tweaking.

BTW are the 10-uf capacitor leakage and gate current really low enough to use a gigaohm gate leak resistor-- 1pA ==> 1 mV? And do you really want a 3 hour time constant on your bias circuit? Oh, and you have two nearly perfect integrators in your dc feedback loop, which will cause nasty behaviour.

Cheers,

Phil Hobbs

How about a transformer?

John

the

he

(due

shift

Perhaps a resistor in series with the output opamp feedback capacitor=20 could cancel one of those poles.

So where are the natural poles in this circuit, not counting the one at zero for the output integrator? I would put the zero at the lowest one of these poles. Setting this feedback zero would also probably include increasing the size of the integrator capacitor, to reduce the low frequency gain so that the second pole occurs beyond unity gain.

Well, your amp is going to take a long time to stabilize when you turn it on, just based on that 10,000 second time constant. With a 15V power supply, the bias loop will slew at (at most) 15 mV/s.

If all you want is a noise measurement, you can use the correlation trick: put two amplifiers on it, and cross-correlate their outputs. The amplifier noise goes away and the true signal survives. Gives you a nice mean-square noise measurement. You can set the measurement bandwidth and integration time separately to get the measurement you need--e.g. you can measure the noise in 1 MHz bandwidth but integrate for 1 second, and get a 60 dB noise improvement.

You can get rid of the thermal tails pretty well by biasing the JFETs at their peak power points.

Alternatively, you might consider turning the problem inside out: use a normal op amp to do most of the job and use the JFETs to measure its differential input voltage, so that the *JFETs* are the feedforward path. If you can match the gains of two signal paths accurately, you can get the low noise of the JFETs and the stability of a normal op amp.

The noise suppression you can get with that trick will be limited by the gain matching and phase shift between the JFET feedforward path and the normal op amp path.

(Anybody done that before? I might have invented it just now.)

Cheers,

Phil Hobbs

Challenging!

I don't know if you can meet the noise specs by going down this pathway, but if the series RC shunting the input adds too much noise, I think you're going to have to bootstrap your input circuit to get rid of the negative RC Zin. This will have to operate at high speed -- not at the slow speed of the feedback loop. Of course there are limits to this approach as well, but with the right topology you may be able to use a pure capacitance between J1's gate and an appropriate virtual ground input node to provide a high frequency boost to J1's source. This has been done, for example, in a few oscilloscope vertical inputs to provide a wider-band input while reducing the dribble-up behavior of real follower circuits which have capacitive loading.

Did you say anywhere what the spec had to be for input capacitance? Perhaps a bit more HF energy can be stolen from the input? Some other games might be played if that is allowed. From your resistor values it looks as though Rin must be high.

Unfortuantely I don't see any way to use the capacitive feed-beside method with your existing topology. It really needs a follower initial input stage.

This fixes your Zin problem but reaching your noise target will be fun. I confess I haven't gone through the numbers to determine whether that is possible with such a different structure. Good luck!

-frank

Why do you need BW to 1 MHz to check a power supply output?

Mark

Thanks Phil. Comments inserted below.

"Phil Hobbs" a écrit dans le message de news: snipped-for-privacy@electro>

(due

shift

Yes.

Which virtual ground are you speaking about? The whole preamplifier is non-inverting.

Hmmm, feedforward is one thing I forgot to think about. I can smell some interesting idea here but right now I fail to see exactly what you have in mind. Can you sketch something?

One thing I can't do is getting the Jfets out of the feedback loop. The preamplifier will have 2 purposes:

I've measured some of the Jfets at under 2pA gate leakage under these conditions, much better than the given specs and this is for a few boxes, so that's OK for me. I was pleasently surprised because these are pretty big transistors and this will simplify my already enough complicated life.

The 10uF are specified at 25000s minimum time constant, i.e. 2.5 gigaohm. The input DC component is about 10V and I've again measured some samples much better. Again I can select so it's OK too.

And do you really

An unfortunate side effect of the low frequency requirements. I've not shown some speed up circuitry which was not relevant to the pb.

The 10uF is mandatory because of the gate shot noise rising the input noise at low frequency, and the bias resistor has to be 1Gohm because I obviously don't want its current noise be greater than the gate noise current.

Oops, yes I obviously missed a zero somewhere :-)

"John Larkin" a écrit dans le message de news: snipped-for-privacy@4ax.com...

the

(due

shift

Yep. It indeed increases noise by a sqrt(2) factor and makes me double the Fets number to regain it... and worsens the negative resistance number by the same factor as a side effect :-)

Anyway some other problems make this a preferred solution: A single branch input stage will have to either have its source current provided by the feed back network (if one use feedback around it), or compensated with a current source.

The preamplifier will have 2 purposes (and 2 modes):

2) measure the supply transient recovery to an injected charge. The measured recovery is about 200nV, so expected aberrations (electric and thermal) should be lower than 50nV,... excluding noise :-) Unfortunatly the initial transient can be a few 100mV, up to about half a volt. I obviously can't have the lower feedback resistor (0.2R!) stand half a volt (and I want the power to be limited: low noise switching supply for the isolated input stages, low thermal convection noise and blah...), so in this mode, where I can average out the noise, the feedback network is switched to a more current friendly 100R/2.7K per transistor, which will represent a manageable total 20-30mA at 0.5V input. This feedback network obviously can't provide the 100mA transistor current, so a compensation current source would be required, with a too big impact on LF noise.

Another pb for the single sided solution is that the source will have to be servoed at 0V (current in the 0.2R fb resistor) which will make the gate potential between -0.1/-0.5V, with potential leakage problems in the protection device. A few mV is all I can accept here.

Yet another pb is the looong input time constant and the diff input stage will help slow thermal drift rejection.

And... and...

Probably something like this. As I can't have any series resistance, at least at the begining of an input event, the diodes will have to cope with high current pulses.

----+--+--------+------ | | | V - | - ^ | | | /| | | | /+|-' +--+---< | | | \\-|-. | | \\| | | +--------+-----> current limiting switch command | | V - - ^ | | GND GND

And also probably some switched current limiting resistor (I can have a permanent one due the noise specs), because I have to protect the supply under test from the 10uF cap charge (and discharge). Unless I discover the miraculous depletion transistor with ultra high Gfs and low Idss. Maybe I can have my little daughter write this down on her letter to SK, but I guess she'll fell upset if I have that nice transistor and something else is missing.

Do you know such a beast? :-)

Hmmm, the IF3601-02 I have measure 1.9ohm RDSon. Maybe I should look a bit further, but not too much hope...

the

I don't know why but some messages I answer are not quoted so I have to manually add the quote sign, like below, to keep the message understandable. Anybody knows why?

I've first thought of this, but this is just pushing up the GBW product and when the loop gain falls again, guess what... On the same note I've thought of limiting the gain in the pass band to have it uniform, like loopgain = constant (50) from LF to the corner freq. But the outcome is the same at HF.

"Frank Miles" a écrit dans le message de news:dmi624$fs0$ snipped-for-privacy@gnus01.u.washington.edu...

wrote:

the

(due

shift

Yup. From the whole bunch of pb I could list I'm pretty safe to say that this is probably the limit of what's doable at room temperature.

you're

RC

but

J1's

frequency

oscilloscope

dribble-up

Hmmm, now that sounds interesting. That really is a clever trick, if I understood correctly what you meant. Do you have any specific scope reference or schematics to look at?

Plus, in my case, the following current mirror and summing, neutralize this current injection (from the loop gain POV). Really nice!

Perhaps

though

Not at all (well in AC). The source is low impedance (indeed, it is a low noise one). The (almost only) limiting factor is the cable series inductance, up to 1 meter length requested, but I hope I can cut this by half. What other nice thing do you have in mind? I've made me curious :-)

For the high value resistors, as I explained in my answer to Phil Hobbs, the

with

Maybe I can see some solutions.

Time to check...

"John Larkin" a écrit dans le message de news: snipped-for-privacy@4ax.com...

measured

and

is

I've seen it. Unfortunatly its nasty input impedance, 3R at 1Hz, 0.2R at

I wish it would. Well, in fact no: No pb, no contract... :-)

measured

and

is

I don't remember if I've already said this, but I have a fast settling mode to keep this time in the seconds area. The only unknown is dielectric absorption, but a quick check will say all.

I remember you already mentioned this but we also want the spectral density repartition in order to be able to diagnose the causes.

Already done. I also wish I could bias them at their temperature compensation point but the high current value render this impractical :-(

Again I'm not sure I see all the details of what you have in mind. Can you elaborate? But wait... Hmmm, you're giving me another idea, or maybe the same, just pushed a bit further, or presented differently... If I reduce the overall GBW product I rise the resistance negative part and also reduce the maximum possible frequency of oscillation, hence increase cable inductance tolerance (is this enough, I'll have to check this point). Combined with feedforwarding the JFETs signal we could hold a good starting solution. Combining all this with a bandwidth limited (since we have ffwd) version of the Frank Miles' "source boost" trick to get rid of the last bit of negative resistance and it could well be a perfect match to what I looked for.

I'll look into all that tomorrow. It's time to bed now.

"Mark" a écrit dans le message de news: snipped-for-privacy@o13g2000cwo.googlegroups.com...

Yes, why...

Well, because... :-)

Seriously, because those power supplies are part of an ultra sensitive high definition, real time, video imaging system where some minor aspects of noise have huge impact on the image quality. Spatial and temporal coherency of noise, as sampled by the imager, is of primary concern and effects well below an LSB of the 16b ADCs are visible and annoying. And when the final customer pays $5M for one system he simply wants the very best quality :-)

-- Thanks, Fred.

ok, so this is not for an audio mic pre....so ultra low distortion is not a requirement

so what you need is a 50 Ohm amplifer with BW from say 10kHz to 1 MHz with a low noise figure?? They make amplifiers with < 1 dB noise figure at 1 GHz these days.

So why have the big feedback loop which is creating your instability problem and cannot help noise figure?

How about a J310 Nch JFET in common gate, really simple and low noise

Also I would think that a passive LC filter would be VERY effective at reducing the noise out of a power supply in the 1 MHz region...

and if it is a switching supply, I cannot imagine that the random noise is a bigger problem compared to the switching freq..

if it is a linear PSU , a few sections of passive filter should take the random noise down to the thermal noise floor..

what am I missing?

Mark