x86 move multiple

A big truck is great when you want to move lots of heavy stuff, no one expects it go around corners like a racecar

-Lasse

It takes about a microsecond to do anything over PCI Express, and the interface complexity is impressive. I don't know the minimum transaction time for USB, but it must be a lot more. What was the basic i/o time on ISA? It was under a microsecond, I think, even on an

Pity that a modern x86, with a thousand or two pins, doesn't have a usable 8-bit parallel port, or even a few pins worth of uncommitted SPI.

Have you ever read the original 488 spec document? It's insane. The state diagrams are boggling, and the verbiage is weird: I read it for a while before I figured out that the word "message" referred to a simple logic level on a wire.

you

how

the basic timing in USB is 1ms

ISA bus 8MHz and needed a couple of clocks per access from what I remember from many years ago playing with the parallel port ,which was basically a register on the ISA bus, you could toggle a pin at maybe 1MHz

I think MACH3 (a cnc controller), can control steppers at up to something like 100KHz on and old school parallelport under windows

I believe it has a I2C port for memory and stuff on the motherboard is probably part of the chips set just like pretty much everything else

I sure it done for a reason, not much point in slowing down a 3GHz cpu just to get a few io pins, when 10 out 10 will be running an OS that adds many ms latency anyway

-Lasse

Now, the original parallel port was of course a couple gates on the ISA bus. In later days, it was placed on an ISA bridge, and chucked inside an ASIC or whatever the chipset happened to be. Later still, actual PCI parallel port devices showed up, often also in the chipset (IIRC, my desktop computer shows its parallel port is on the PCI bus, not the ISA bridge -- which is still used for the ancient IBM-compatible hardware: DMA controller, PIT (system clock) and so on). Now, PCI runs faster than ISA... does this mean a PCI parallel port is clocked at 33MHz, or is it clocked down to 8MHz or less to maintain timing compatibility? If so, does it enforce wait states so that data can't be shoved at it too fast?

Disclaimer, this has nothing to do with PCIe.

Tim

If you want fast from a modern parallel port use ECP which is a DMA mode, but in this mode it's not much use as GPIO.

parallel port clocking is done cooperatively (both ends of the link control the rate), I have not tried to measure the max speed.

DS:SI = Source ES:DI = Destination CX = count (if REP prefix used)

IIRC, in processors after the '286 it's slower than the individual components (read-write).

Well since the 8086 days there has bees MOVSB/MOVSW opcodes. They take a bit of setup though. They use DS/SI, ES/DI, and D registers IIRC.

?-)

Hmmm. Do you have a copy? Do you know where to get one?

?-)