What's the hi-side current sense chip du jour?

Nope, just FETs to VCC and GND. In the single-digit ohms league.

Send me your schematic privately, and I'll check it out with PSpice.

...Jim Thompson

After that last post I realized that almost exactly 4 years ago (5/15/2005) this gate charge issue was discussed here, many models were compared to Win Hill's measured data.

A quick check, with an IRF120, gate driven by 22mA, "flat spot" voltage on the gate is 53ns wide (4.613V -> 4.651V !-)

...Jim Thompson

Since when did Joerg have a project with a budget that included a lunch of Duck and Rum? :-)

When I win the lottery I'll ask him to design something. If he accepts, he gets a fat fee, a huge budget, no space constraints _and_ lunch!

Ed

I'll dig through it, maybe one of them is ok to send. Hoping I'll get through the tattooed bouncer at your email gate ;-)

Ok, that's almost flat.

Done. Found a non-conf one.

Just had lunch. Olive loaf on German sourdough, some Braunschweiger liver pate, Havarti cheese, Italian salami and Polish dill pickles. Yummy.

If you throw in a few margaritas as well I'll take it :-)

I was just seeing what current into an IRF120 would produce ~50ns.

Reality reaches out and bites...

Si4480DY gate is rated 30nC (typical).

LTC1871 risetime spec implies 833mA pull-up.

t = Q/I... 30nC/833mA = 36ns

Du-u-u-u-u-uh ;-)

...Jim Thompson

See my other post ;-)

...Jim Thompson

Ah, ok.

It pulls up under 4ohms and down with 2ohms. In a real circuit it does a lot better.

What I never really understand are two things: Why some PWM chips limit the drive voltage to 7V or so, and why they don't leave an option to swing negative to clean out the gate (ok, that one may be a process challenge).

Where allowed I usually bypass the internal LDO and feed that node separately so I can switch with mucho more gusto. But why don't they provide that internally in the first place? If I had my druthers I'd do a semi-discrete design again, with a 5-10 amp CMOS driver chip. Could also put one in between the PWM chip and the FET but then its prop delay messes with the Rdson-sense circuitry.

Naaaah! It's CMOS. It has an IDSS limit. The data sheet says pull-down is slower than pull-up, matches your simulation.

I wouldn't know, I don't design jelly bean stuff, just ASIC's.

To go below ground you'd need a "pump". But think about your statement... got you again ;-)

Again, I wouldn't know, I don't design jelly bean stuff, just ASIC's.

Do you have second sources for your LTC parts ?:-)

...Jim Thompson

Naaah :-)

Datasheet sez 17nsec pull up for a 3300pF FET, 8nsec down, bottom of page 4:

Hey, this ain't jelly-bean stuff ...

Got me? Where?

Sure you need a pump but that's no big deal. Nearly all buck chips have one (upwards though). I wouldn't even mind another wee inductor, diode and cap, if I just could have more gusto for the FET drive. I mean, if the datasheet says +/-20V abs max like they do for most big FETs then it would be cool to swing it at least +/-12V or so.

There are no 2nd sources for pretty much any modern PWM chip. Not too important in this case. If it were I'd have to do it discrete like usual but that costs a lot more design time. LTC has a very good reputation for not obsoleting parts out of the blue. If I must use single-source I really like them. Plus they furnish LTSpice plug-and-play models for most of their parts which seriously cuts design hours for my clients. Of course the models aren't always true to real life in all points. Such as pedestals :-)

I went by the chart on p5 to estimate IDSS, but I reversed pull-up/pull-down.

But it doesn't say 3300pF _FET_, it says "capacitance". And it gives

But I'm still in the ball park, particularly with the "funny" load ;-)

limit

Sure it is. Isn't under $5 jelly-bean ?:-)

It's a pull-down CURRENT... CMOS, remember?

The "pedestal" effect is in the PowerMOS model... gate charge.

...Jim Thompson

Well, that's anyone's guess. Binary file, can't decipher it easily.

Nah, jelly-bean is when none of the parts costs more than 25c or so. On this design I am still shooting to stay under 70% of allowed BOM budget. Makes clients happy :-)

Well, everything in electical life is a current :-)

In the end it'll probably be the usual logic-gate style pair, activated bang-bang style so you end up having something close to 2ohms internal Rdson to GND.

To say it Corleone-style, I need to make that go away. Bigger guns in the PWM chip -> other PWM chip.

LTspice uses encrypted models ??

For the controller or for the PowerMOS?

You can't make it go away. The pedestal time will halve every time you double the drive capability. Doesn't sound like a very pleasant exercise :-(

...Jim Thompson

I like LM5112 as a gate driver. Lots of current, lots of swing, *and* it can pull the gate negative if you want to. I've done switching regs with the 5112 and a few discretes, no other controller chip at all. Its schmitt trigger input can be used to make it an oscillator/comparator.

John

That certainly would be my preference. I derive no pleasure from having someone else determine my architecture ;-)

...Jim Thompson

Probably not, haven't looked too closely but Notepad spits out Swahili when opening the *.sub file.

No, the FET is a regular ASCII file.

It ain't fun because these are all current-mode controlled converters and a driver adds prop delay. But man's got to do what man's got to do.

For amusement, simulate with drain of output device tied directly to VDD.

Probably Miller effect is aggravating the gate charge condition.

...Jim Thompson