Verilog style question

Phil Hobbs · 2014-04-11T19:45:26+00:00

Hi, all, I'm writing my first bit of mildly nontrivial Verilog. It's a controller for a sort of combination boxcar and lock-in, with a few bells and whistles. (The lock-in runs for exactly N cycles, with nonoverlapping switch waveforms with enough dead zone for the amps to settle, and then holds the final value.) To make the control inputs well-behaved, I'd like to make them ones-catching, i.e. clock 1 into a register when they arrive, and reset it when a state machine gets to the right point. So I had a bunch of things like this: always@(posedge reset) resetLatch

Apr 11, 2014 21 Replies

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josephkk 12 years ago

I would probably try to define a state machine for it. There are natural translation to verilog from there.

?-)

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Lasse Langwadt Christensen 12 years ago

I think this would work

always@(posedge clk or posedge Go) if(Go) Go_latch customers as being pretty old-school, and besides, it takes a lot of

it is like assembly programming, it can be a fun challenge in a jigsaw puzzle kinda way, but in most cases it isn't very productive

I believe there used to be symbols for most of the standard 74xx parts you could use in a schematic and synthesize, but schematics is passe and most of the async stuff wouldn't be good fit for the hardware meant for synchronous design

-Lasse

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