I would probably try to define a state machine for it. There are natural translation to verilog from there.
?-)
- Vote on answer
- posted
10 years ago
Verilog style question
Loading thread data ...
- Vote on answer
- posted
10 years ago
t e
nd
al
I think this would work
always@(posedge clk or posedge Go) if(Go) Go_latch customers as being pretty old-school, and besides, it takes a lot of
it is like assembly programming, it can be a fun challenge in a jigsaw puzzle kinda way, but in most cases it isn't very productive
I believe there used to be symbols for most of the standard 74xx parts you could use in a schematic and synthesize, but schematics is passe and most of the async stuff wouldn't be good fit for the hardware meant for synchronous design
-Lasse