I like them because they're easy to understand, friendly to comment, usually are bug-free, and keep fanout down, which helps speed. It's easy to duplicate state flops off-to-the-side (two-hot design?) to reduce fanout with no speed penalty. I should note that I do most logic design as schematics and pretty much expect the FPGA software to plop down a flipflop where I tell it to.
I don't mind trusting a compiler to reduce combinatorial logic for me, but I still design the logic with the FPGA cell architecture in the back of my head, so I pretty much know what's going to happen and how deep the logic will have to be.
John