Hi,
While searching for USB IP resources on the net I came across USB PHY cores in verilog.
1) Why is it neessary to seperate USB controller and PHY in two different cores? It may be necessary for 3.0 due to higher speeds but what is the need for 1.1 and 2.0?
2) If USB PHY is a mixed (Analog & Digital) solution how can it be offered only in verilog as developer claims? How can a mixed core (GDSII and HDL) be implemented in FPGA?
3) If I have the USB and USB PHY cores seperately how do I implement in FPGA and use/test it?
See the description of USB 1.1 PHY core from
formatting link
.Thanks in advance. br
******************************************************************************************************************************** "USB 1.1 PhyUSB 1.1 Physical Interface core. This core provides all functions essential to interface to the USB 1.1 bus. This includes serial/parallel conversion, bit stuffing and unstuffing, NRZI encoding and decoding and a DPLL. It comes with a industry standard UTMI interface for easy portability
Sample Implementation Results Technology Area Speed Xilinx Spartan 2 xc2s50-6 111 LUTs (30%) > 50 MHz
Currently this IP Core is available in Verilog only."
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