Unconnected part LTSpice seems to need (weird ...)

No, this IC will be totally new turf. Reason for my sims is the we now have to take care of the design of the connecting electronics while it'll be in production. That way it'll all come together at roughly the same time.

In the end we'll have to live with whatever the IC has, there is practically no space for any other parts to the right of the TX line.

I might. But we can't place diodes because it's multi-channel and that would be lots of parts in a space that isn't there :-)

It's no problem because the signals going up can be shaped accordingly. I was just wondering why LTSpice is producing inconsistent results here. It's ok if it runs into a dead end with some calcs but I'd have thought that would caused the usual error messages. Yet I get none of those.

--
Regards, Joerg

http://www.analogconsultants.com/

mismatch.

of

Strange thing is, with the non-lossy TX line and disconnected diode I do not get any mangled pulses. Only when I remove the disconnected diode the first pulse gets mangled. Since it was already disconnected to begin with that should not make one iota of a difference. But it does. Maybe it's all different between versions, I use 4.07e.

--
Regards, Joerg

http://www.analogconsultants.com/

That's what I saw, maybe I didn't make it clear enough.

This is 4.00C

I'll try extracting the Spice netlist and see if I can get it to run in good ol' Spice 3f4.

All I got left with using the lossy line model was all on the first pulse, and was traceable to source termination. With 100% absorption of reflected energy it was all clean.

--
"For a successful technology, reality must take precedence 
over public relations, for nature cannot be fooled."
                                       (Richard Feynman)

Thing is, that won't be realistic in real life. Small transmission lines such as coaxes have quite a bit of tolerance on the impedance, sometimes as much as +/-10%. We'll have to live with that.

--
Regards, Joerg

http://www.analogconsultants.com/

Stepping the source resistance or the line Zo +/-10% don't look good.

--
"For a successful technology, reality must take precedence 
over public relations, for nature cannot be fooled."
                                       (Richard Feynman)

I did that and it looks quite ok. The main thing in any IC is to not exceed abs max for peak voltage because then ... pop ... *PHUT*

--
Regards, Joerg

http://www.analogconsultants.com/

of course it should! You floating node makes for an ill conditionned matrix. Be thankful to Ltspice that it gives you some not too idiotic result. Most others would simply have returned an error message. You can circumvent that in most spices with either a gmin or an rshunt option which will make you node non floating.

I suppose that ltspice just do that silently (or it coud not give you any result).

Now, default gmin or rshunt are set to 10^12 ohm and solving such extrem matrices can lead to spurious errors. That coupled with the 1000k resistor that ties your tline to ground gives you the bad spikes. Delete the diode and, since you have no more dangling node, the matrix is much better conditionned and the solver has no reason to invent anything anymore.

With your circuit, just reduce your 1000K to 1K, or replace it by a short - which changes nothing since a spice tline is all but your expected 4 feets coax (you need 2 tlines for that) - and your spike vanishes. Another way is to set reltol (from the spice tab, not the compression tab) to 100u or better. Yet another way is to change the integration method from trapezoidal to gear which, as a general rule, is slightly less accurate but provides some natural damping to the solving process and most of the times prevents such artefacts to occur.

Maybe I stumbled upon a bug here and if this is corroborated

Not at all. That's classic spice stuff :-)

That is what a simulator should never do, silently adding stuff or connections. Very dangerous turf. It was supposed to give an error with the open diode. But it didn't.

All that is what I also thought. Until I deleted that diode, upon which the simulator fell flat on its belly. Rather unexpectedly.

Indeed, thanks! If I reduce it to 100K it works.

Strange, I purposely chose 1M instead of several G. Wouldn't have thought 1M is too extreme for SPICE. But it looks like in this case it is.

--
Regards, Joerg

http://www.analogconsultants.com/

It's not the 1M resistor on its own. Your circuit is extremly weird, spice wise...

You combine a lossless tline, extremely fast switching (sw switched are particularly weird), no damping anywhere, floating nodes, and so on. What do you expect?

For example, just load your tline with a 0.1p cap and all returns to normal. Ideal, non physical schematics are often a clear path to funny results...

You obviously haven't lived enough with spice ;-)

-- thanks, Fred.

Oh, thought you did that. You *can't* simulate a coax line with its four nodes all distinct with a single tline. You need two, or you result will be anything but realistic. Either you tie both end of the shield to gnd in which case it's OK with a single line. But if you want the other end floated you need two 'stacked' tlines to model the two modes:

- one for shield to gnd ('ambiant')

- one for center conductor to shield.

Then you don't need your resistor from 'shield' to gnd anymore, which BTW is just a convergence/matrix conditionning kludge but won't make your tline physical.

-- Thanks, Fred

I know it's weird but it is mimicking pretty exactly what the IC will do later. And those work, it's not the first one I did. I did have to simplify a lot of things, there's a whole lot more stuff like Rdson mimicking on there but not at liberty to post.

That it works, like the real thing :-)

Oh, I have, but driven it to the limits at times. Fact is, SPICE is not supposed to quietly and secretly add stuff. It obviously must have in this case, as evidenced by the fact that two identical circuits produce different results. If an algorithm got to the edge I'd expect a convergence warning or something.

Sure, I can make it work with added parts. The point of my question was that it treats a disconnected part differently than the same part deleted. And that's not supposed to happen. The really strange thing is that obviously people with other versions of the program have also see this weirdness, but with even other results. Sumpthin' ain't right.

--
Regards, Joerg

http://www.analogconsultants.com/

I have done it the same way on the previous project and the results were almost identical between sim and measurement, as if I had painted the SPICE sim onto the scope screen. But that was Microsim PSpice (before Cadence bought them, in the good old DOS days). We were told before that it couldn't be done and for me that statement is always an incredible motivator :-)

In general with this sort of situation you lose transmit level if the source resistance is too high. When it gets too low you have to be careful because then leading edge spikes can exceed abs max on the chip. But there's some nifty ways to detect that condition at a modest pulse amplitude, from echoes.

--
Regards, Joerg

http://www.analogconsultants.com/

It's probably as simple as a timestep set too large... or your Adobe is getting gout again ;-) ...Jim Thompson

[On the Road, in New York]

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

[...]

It usually sez it in an error box when that happens. My point was that it seems to treat a diode with one electrode disconnected differently than the diode not being there at all. This defies logic.

And I am not using Adobe anymore so those problems are things of the past. Since my Orcad rental license has expired that means no crashes no more on this here computation machine :-)

Must be a loooong road there :-)

Did you pick up on the accent already, during your woik in Nu Yohk?

--
Regards, Joerg

http://www.analogconsultants.com/

Rained more yesterday than in a year and a half in Arizona :-(

No, but picked up a criminal at some restaurant, copied my AMEX numbers and tried to buy $800 worth of jewelry on-line... but he got cut off at the pass... store was suspicious and called AMEX security, who called me. New card here tomorrow. ...Jim Thompson

[On the Road, in New York]

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

I am always amazed how well spice works these days. Best I can suggest is start deleting other nodes and components to try and get a minimum size network that shows the problem and can be disclosed publicly.

If you only connect the anode but to the wrong side of where the diode goes do you get the "anode connected" behaviour or the other one?

Regards, Martin Brown

It doesn't defie logic at all when you don't refuse to understand that once you put a diode somewhere, with at least a connection to the network, it

*is* included in the solving matrix. And doing so with one unconnected side you *are* asking spice to solve an ill conditionned system. Period. And ill conditionned systems can give you pretty chaotic results (change some starting conditions just a little bit and you have 'unpredictable' widely different result). No surprise there.

It's not spice fault, it's you that don't see the implication of what you're doing, as I already said.

-- Thanks, Fred.

If it has problems with the matrix, then way doesn't it issue a warning?

--
Regards, Joerg

http://www.analogconsultants.com/

I did that a couple of days ago, it's attached again.

Then the sim completely bombed on me. Like Fred said, it is possible that SPICE incudes this diode in the matrix and chokes on it. But then it's supposed to issue an error message and not just fly straight into terrain.

Regards,

Joerg

Version 4 SHEET 1 2324 792 WIRE 1504 -224 1040 -224 WIRE 1904 -224 1584 -224 WIRE 1904 -192 1904 -224 WIRE 448 32 352 32 WIRE 848 32 528 32 WIRE 1040 32 1040 -224 WIRE 1040 32 944 32 WIRE 1200 32 1040 32 WIRE 1264 32 1200 32 WIRE 1376 32 1344 32 WIRE 1648 32 1456 32 WIRE 1760 32 1648 32 WIRE 1952 32 1760 32 WIRE 1648 48 1648 32 WIRE 848 64 784 64 WIRE 1040 64 944 64 WIRE 1568 64 1568 -176 WIRE 1600 64 1568 64 WIRE 352 80 352 32 WIRE 784 80 784 64 WIRE 1200 112 1200 32 WIRE 1328 112 1328 80 WIRE 1328 112 1200 112 WIRE 1520 112 1520 -176 WIRE 1520 112 1328 112 WIRE 1600 112 1520 112 WIRE 1952 128 1952 32 WIRE 1648 144 1648 128 WIRE 1760 144 1760 32 WIRE 352 176 352 160 WIRE 1040 320 1040 64 WIRE 1120 320 1120 224 WIRE 1120 320 1040 320 WIRE 1280 320 1280 80 WIRE 1280 320 1120 320 WIRE 1568 320 1568 64 WIRE 1568 320 1280 320 WIRE 1648 320 1648 224 WIRE 1648 320 1568 320 WIRE 1760 320 1760 208 WIRE 1760 320 1648 320 WIRE 1904 320 1904 -112 WIRE 1904 320 1760 320 WIRE 1952 320 1952 192 WIRE 1952 320 1904 320 WIRE 1040 336 1040 320 WIRE 1040 432 1040 416 FLAG 784 80 0 FLAG 1040 432 0 FLAG 352 176 0 SYMBOL cap 1936 128 R0 SYMATTR InstName C1 SYMATTR Value 25p SYMBOL tline 896 48 R0 WINDOW 3 -62 67 Left 0 SYMATTR Value Td=6.25n Z0=50 SYMATTR InstName T1 SYMBOL res 1024 320 R0 SYMATTR InstName R4 SYMATTR Value 1000k SYMBOL res 1632 128 R0 SYMATTR InstName R2 SYMATTR Value 100 SYMBOL sw 1648 32 R0 SYMATTR InstName S1 SYMATTR Value SW1 SYMBOL res 1472 48 M270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R5 SYMATTR Value 25 SYMBOL sw 1248 32 R270 SYMATTR InstName S2 SYMATTR Value SW2 SYMBOL diode 1744 208 M180 WINDOW 0 24 72 Left 0 WINDOW 3 24 0 Left 0 SYMATTR InstName D1 SYMATTR Value MMSD4148 SYMBOL sw 1600 -224 M270 SYMATTR InstName S3 SYMATTR Value SW1 SYMBOL voltage 1904 -208 R0 WINDOW 123 24 132 Left 0 WINDOW 39 24 44 Left 0 WINDOW 3 25 102 Left 0 SYMATTR SpiceLine Rser=20 SYMATTR Value SINE(0 .5 20MEG 0 0 0 500) SYMATTR InstName V4 SYMBOL voltage 352 64 R0 WINDOW 39 24 44 Left 0 WINDOW 3 25 102 Left 0 SYMATTR SpiceLine Rser=1 SYMATTR Value PULSE(0 100 200n 10n 10n 35n 100n 3) SYMATTR Value2 AC 1 SYMATTR InstName V1 SYMBOL res 544 48 M270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R1 SYMATTR Value 50 SYMBOL diode 1104 224 M180 WINDOW 0 24 72 Left 0 WINDOW 3 24 0 Left 0 SYMATTR InstName D2 SYMATTR Value MMSD4148 TEXT 520 -240 Left 0 !.tran 1u TEXT 1144 360 Left 0 ;R4 only for SPICE purposes TEXT 1384 -432 Left 0 !.model SW1 SW(Ron=1Meg Roff=1 Vt=15 Vh=-.4) TEXT 1384 -400 Left 0 !.model SW2 SW(Ron=1 Roff=1Meg Vt=15 Vh=-.4) TEXT 1288 144 Left 0 ;Pass-FET TEXT 1456 200 Left 0 ;Shunt-FET TEXT 1144 392 Left 0 ;Diodes representing substrate paths