Is there any difference in the leakage current if an uncommitted output of a CMOS MCU is set to "1" or "0" ? Is there any rule or the difference is just random depending on the particular part /technology /temperature /voltage / etc. ?
Vladimir Vassilevsky DSP and Mixed Signal Design Consultant
The iffy reliability of anecdotal evidence notwithstanding, I'd say not a significant difference on any given part. Interestingly, a quick search [*] of my local datasheet cache shows that microcontroller datasheets overwhelmingly prefer the term "input leakage" while interface chips and drivers like "output leakage" with the appropriate sign switches.
[*] Against all expectations, it turns out (anecdotal evidence warning) that WinXP's Windows Search app combined with Foxit's PDF ifilter has been running transparently and very handily to make a full-text search of my local datasheet collection. Quite useful. Who'd'a thunk it?-- Rich Webb Norfolk, VA
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I suspect that set to outputs, there would be only internal leakage currents (high or low); set to input, would be asking for trouble in the well documented ways.
?-)
It really depends on what ESD structure is used. Generally an output device is plenty beefy to take a hit. If that is all you have, then it shouldn't matter which level the output pin is at. But some companies are concerned that ESD could couple back into the chip. If the ESD is the poly resistor followed by nfet snapback type buffering the driver, then there is a marginal amount of leakage if the pin is high, due to the snapback device.
An interesting effect of ESD damage to an output device is often the chip still works if damaged, but you created a leakage path from the driver to a rail. So the chip draws a little extra power in operation, but switches just fine. This is tricky to catch, depending on the companies qual flow. For instance, if they just zap chips at different levels then send them back to ATE for go/no-go, the high leakage may not be caught, especially on a mixed signal chip which has a bit of IQ. If the driver pin is tri-state, a curve tracer could pick up the damage. An emission microscope could see the damage, but nobody decaps good units to look.
So the conclusion of all this long winded babbling is don't worry about the intrinsic current (high or low), but use caution in assembly where it can really bite you.
Of course, but you just have to decap the bad ones... :-)
-- Thanks, Fred.
Keerect. ...Jim Thompson
[On the Road, in New York]
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| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
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| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
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I love to cook with wine. Sometimes I even put it in the food.
From old days, I could remember that the P-channel FETs were considerably worse then the N-channels. So, the leakage in "0" is probably higher then the leakage in "1", no?
Vladimir Vassilevsky DSP and Mixed Signal Design Consultant
It may be design-dependent... the sizes of the P and N channel devices can be different. _Most_ MCUs have considerably more drive current available from the N-channel, so one might assume the area of the two are similar, given the 2:1 or 3:1 difference in carrier mobility between holes and electrons. I would guess for such devices it wouldn't make a heck of a lot of difference.
FPGAs sometimes set the uncommitted pins to outputs = zero. The board designer then grounds these pins, lowering the ground impedance. One can tie some to '1' to add Vcc pins, too.
In the "old days" substrates were N-type. Now-a-days the P-Channel device leaks less. ...Jim Thompson
[On the Road, in New York]
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
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