I have a little project am trying to design, and I am running into a little difficulty in the concept stage.
I have a device that needs to consume essentially zero power when shut off. A few nanoamps is fine. The device uses a 6S LiPo battery that must be m onitored during operation to make sure the battery is not discharged beyond critical limits. To this end, the battery is connected to a 6 input digit al battery monitor which constantly monitors the health of each cell. Duri ng operation, the battery monitor consumes an insignificant amount of power , but it is in the milliamp range, making it too large to be able to remain connected when the device is stored for moderately extended period of time .
I solved the problem by using 7 reed relays between the battery and the mon itor, energizing the relays when the main power is switched on. This works perfectly, but there is an issue. Reed relays are comparatively large, an d the resulting design cannot be shrunk down to much less than 3" x 3" afte r adding the additional components.
What I am considering is replacing the reed relays with unity gain operatio nal amplifiers. A pair of TL074CDR op amps is much smaller than the red re lays, and mechanically I should be able to reduce the board to a much small er footprint. The problem is when the mains power is shut off, the op amps will still be attached to ground, while their inputs will still be attache d to various voltages up to 25V with no Vcc. I am thinking this may destro y the JFET inputs of the devices. Looking at the logical design, I'm not s ure, however. Both input sources are attached to the collector of a PNP tr ansistor, which most certainly could carry current to its base, but the bas e is attached to the collector of an NPN transistor which should exhibit a very high impedance when the power is off. The base is also attached to th e bases of a pair of PNP transistors, but those junctions should also offer a very high impedance to ground. The drains of both JFETs are attached to the bases of NPN transistors which offer a fairly low impedance to ground. Given that, I am thinking the JFETs would be destroyed by an input voltag e greater than 15V when the power is shut off.
Am I wrong? If not, is there a different choice of high input impedance op amp that can withstand up to 25V when power is shut off?