Transmission Gate FF

/C is the same as input clock

(1)the gates at the input and also the feedback loop at the output are active if it's high.

(2)When it goes low, the input gets disconnected and the first stage fb loop runs. this gets also routed to the output at the same time. (this is the negative edge trigger)

(1)When it goes back up, the slave loop at the output will hold the value.

ucture and I must be misinterpreting how it works. The device is negative edge triggered but the logic seems to me to be positive edge sensitive.

be accepting input through the gates when the clock is high. The second FF is set to hold it's present value. When the clock drops the first FF hold s it's value while the second FF opens and flow that value to the output.

he reused a diagram from some other document since most FFs are positive ed ge triggered.

iagramId=SCLS801

Looks right to me: External CLK/ is tied to internal C/. C/ goes to the gat e of the D input NFET; C goes to the PFET. So, CLK/ high enables the CMOS s witch.

-Mark

tructure and I must be misinterpreting how it works. The device is negativ e edge triggered but the logic seems to me to be positive edge sensitive.

d be accepting input through the gates when the clock is high. The second FF is set to hold it's present value. When the clock drops the first FF ho lds it's value while the second FF opens and flow that value to the output.

the reused a diagram from some other document since most FFs are positive edge triggered.

Ok, I was missing the fact that the /C was the same as the external clock. Even when it is negative edge, to me it's just the clock rather than clock not.

Thanks.