Transmission Gate FF

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The TI SN74HCS72 has a diagram showing the internal transmission gate struc
ture and I must be misinterpreting how it works.  The device is negative ed
ge triggered but the logic seems to me to be positive edge sensitive.  

For negative edge triggering, the first set of transmission gates should be
 accepting input through the gates when the clock is high.  The second FF i
s set to hold it's present value.  When the clock drops the first FF holds  
it's value while the second FF opens and flow that value to the output.  

Here's the diagram.  Tell me this isn't positive edge triggered!  Maybe the
 reused a diagram from some other document since most FFs are positive edge
 triggered.  

http://www.ti.com/data-sheets/diagram.tsp?genericPartNumber=SN74HCS72&dia
gramId=SCLS801

Full data sheet here.  

http://www.ti.com/lit/ds/symlink/sn74hcs72.pdf?ts15%88731244057

--  

  Rick C.

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Re: Transmission Gate FF
On 05/06/2020 04:42 AM, Ricky C wrote:
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/C is the same as input clock

(1)the gates at the input and also the  feedback loop at the output  
are active if it's high.

(2)When it goes low, the input gets disconnected and the first stage  
fb loop runs. this gets also routed to the output at the same time.  
(this is the negative edge trigger)

(1)When it goes back up, the slave loop at the output will hold the value.



Re: Transmission Gate FF
On Wednesday, May 6, 2020 at 12:13:44 AM UTC-4, Johann Klammer wrote:
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tructure and I must be misinterpreting how it works.  The device is negativ
e edge triggered but the logic seems to me to be positive edge sensitive.
  
Quoted text here. Click to load it
d be accepting input through the gates when the clock is high.  The second  
FF is set to hold it's present value.  When the clock drops the first FF ho
lds it's value while the second FF opens and flow that value to the output.
  
Quoted text here. Click to load it
 the reused a diagram from some other document since most FFs are positive  
edge triggered.  
Quoted text here. Click to load it
&diagramId=SCLS801
Quoted text here. Click to load it
.

Ok, I was missing the fact that the /C was the same as the external clock.  
 Even when it is negative edge, to me it's just the clock rather than clock
 not.  

Thanks.  

--  

  Rick C.

  + Get 1,000 miles of free Supercharging
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Re: Transmission Gate FF
On Tuesday, May 5, 2020 at 7:42:31 PM UTC-7, Ricky C wrote:
Quoted text here. Click to load it
ucture and I must be misinterpreting how it works.  The device is negative  
edge triggered but the logic seems to me to be positive edge sensitive.  
Quoted text here. Click to load it
be accepting input through the gates when the clock is high.  The second FF
 is set to hold it's present value.  When the clock drops the first FF hold
s it's value while the second FF opens and flow that value to the output.  
  
Quoted text here. Click to load it
he reused a diagram from some other document since most FFs are positive ed
ge triggered.  
Quoted text here. Click to load it
iagramId=SCLS801
Quoted text here. Click to load it

Looks right to me: External CLK/ is tied to internal C/. C/ goes to the gat
e of the D input NFET; C goes to the PFET. So, CLK/ high enables the CMOS s
witch.

-Mark

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