Doesn't need to be. The probes I have need a few gold plated pads in a specific pattern on the PCB and 2 holes. Loading is less than 0.7pf. But the probe connection needs to be designed in the PCB.
You didn't say that before :-)
I'd do the math first. Cumbersome and it takes some arm wrestling with the FPGA tools (Xilinx at least) to get real numbers on minimum/maximum setup and hold requirements in worst case conditions. Many years ago I designed an FPGA DDR interface that way. Verification of timing was more or less a formality.
I have been doing the same with FPGA designs. Have some pins for debug and route signals to the pins. Some of my designs have a debug output mux which allows the firmware to select which signals are on the debug pins. No need to compile special test versions.