Switchercadlll - Weird simulation outcome

The links don't work for me but I'll make a guess.

You are doing a .AC on the circuit. One of the characteristics of this is that it doesn't jump up and yell oscillator when you feed it one. About the only indication you will get is an imposible phase shift.

.TRAN will model oscillators as oscillating.

Hello Ken,

Plus you may have to jump-start them or inject a little noise.

Regards, Joerg

The circuit is a bandpass filter and the input is swept frequency.

Hello Boris,

Then AC analysis should be fine.

Regards, Joerg

So why do two circuits give identical results?

Regards,

Boris Mohar

Got Knock? - see: Viatrack Printed Circuit Designs (among other things)

void _-void-_ in the obvious place

Hello Boris,

To get a time domain analysis you'd have to add the .TRAN portion. The start of an oscillation is a time domain process. AC analysis assumes a momentary (in this case stable) state.

Regards, Joerg

Pardon if my ignorance is showing but this is a bandpass filter and not an oscillator. I am sweeping the input over the desired frequency range and in both cases the output of the filter is same.

Hello Boris,

Well, yes, but when you had flipped the input pins the thing would most likely become unstable. This may or may not show, depending on which parts of the SPICE analysis you had turned off.

A pure AC analysis can make a wrong circuit seem to work just as intended, or the same way if it were done correctly. AC does not look at the circuit's behavior over time. That's why SPICE can be dangerous.

Regards, Joerg

Hi Boris, You haven't posted the circuit, so it is hard to tell for sure. But, this is some of the reasons I have seen this sort of thing.

1. You haven't placed a ground on the design. There is a ground in the opamp model you are using, but that isn't very useful outside, so you aren't seeing good results.
2. You placed a ground, but the waveforms you are viewing are not from the nodes you thought they were. You are perhaps viewing the input, and the input through a single resistor/cap, but not the output of the circuit.
3. You have grounded the design, you are looking at the input, but what you didn't realize is that, the way you have everything hooked up, they are actually identical in operation. They just appear different because you moved components around.

Now, if you see a theme, it is that you have probably done some type of pilot error. If you are just learning simulation, then you are not alone. I have seen thousands of basic mistakes like I just mentioned, and I still see new ones every so often.

One thing to do, is to do the .tran analysis. This can sometimes make what you are looking at or doing a lot more apparent. Also, you can post the text of the design here in the group, and we can look at it.

Charlie

an

and in

circuit.

Hello Charlie, none of the above applies. It's really circuit theory which leads to this "strange" result. In reality the opamp output would go to the rail because of noise voltage, but in theory there is an ouput voltage very close to the normal case which fulfills all equations. I coudn't find my previous calculation, but I posted it not a long time ago.

This "wrong" result can happen in SPICE with .OP, .DC and .AC simulation, but not with .TRAN.

Best regards, Helmut

"Helmut Sennewald" schrieb im Newsbeitrag news:dsjbtl$ts8$03$ snipped-for-privacy@news.t-online.com...

not

ago.

An earlier posting about this matter:

... My circuit is an amplifier(E-source) in an inverting circuit, but by mistake the resistors are connected to the positive input. LTspice and any other SPICE will find a solution which is mathematically correct, but you will be unable to reproduce that with any real circuit. The calculated ouput voltage is

-1.0002V with the wrong circuit and -0.9998V with the correct inverting circuit.

Again, the math done by SPICE is correct in both cases! Everybody would say the inputs are wrongly connected, but SPICE is so clever and finds a solution you never have seen in any book! Patent pending! :) ...

R2 R1 in ___ N001 ___ V1 -------o-----------o----out (1V) | | (-1.0002V) | --- | ---|+ |-------- ---|- |-- v=10000 _|_ --- _|_ - E1 -

This would be the correct circuit.

R2 R1 in ___ N001 ___ V1 -------o-----------o----out (1V) | | (-0.9998V) | --- | ---|- |-------- ---|+ |-- v=10000 _|_ --- _|_ - E1 -

The result(V(out)=-1.0002V) from all SPICE programs.

--- Operating Point ---

V(out): -1.0002 voltage V(n001): -0.00010002 voltage V(in): 1 voltage

Here is the netlist for every SPICE.

• D:\Share\strange1.asc E1 out 0 N001 0 10000 R1 out N001 1k R2 in N001 1k V1 in 0 1 .op .end

The schematic file "strange1.asc" for LTspice.

Version 4 SHEET 1 880 680 WIRE -112 128 -112 48 WIRE -112 256 -112 208 WIRE -48 48 -112 48 WIRE 128 48 32 48 WIRE 128 160 128 48 WIRE 192 160 128 160 WIRE 192 256 192 208 WIRE 208 48 128 48 WIRE 240 144 240 112 WIRE 240 256 240 224 WIRE 320 48 288 48 WIRE 320 112 240 112 WIRE 320 112 320 48 WIRE 368 112 320 112 FLAG 192 256 0 FLAG 240 256 0 FLAG -112 256 0 FLAG 368 112 out FLAG -112 48 in SYMBOL e 240 128 R0 SYMATTR InstName E1 SYMATTR Value 10000 SYMBOL res 304 64 M270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL res -64 64 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R2 SYMATTR Value 1k SYMBOL voltage -112 112 R0 SYMATTR InstName V1 SYMATTR Value 1 TEXT -120 -56 Left 0 !.op

The circuits are in Switchercad format (asc)

This is the screen shot of both circuits and the simulation outcome.

I did the tran analysis and revealed that the wrong circuit locked up the output at the rails while the correct version rang for few ms before settling down at the half way point between the plus and ground as expected for a single supply circuit.

Thanks to all for all the help.

Hello Charlie,

It's the jpg link in Boris' initial post.

Yes! A SPICE circuit without a .TRAN analysis is like a car without a steering wheel, unless there are no active components and no nonlinear ones. And no saturating inductors, and...

Regards, Joerg