Stupid 4024 freq divider question (shaft encoder resolution)

Changing ORs to XORs fixes the problem. GOOD solution!

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
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ORs modified to XORs by petrus bitbyter

I'm still not fully awake as I forgot to modify the OR gates into XORs. I did it now.

The lead-lag direction on the outputs does not necessarily changes immediately, but it should do within four clock cycles. Which resembles the codewheel it emulates.

I'd like to simulate too but I have no PSpice available.

If I still made mistakes in this I'll first go search for an alarm clock :)

petrus bitbyter

I read in sci.electronics.design that petrus bitbyter wrote (in ) about 'Stupid 4024 freq divider question (shaft encoder resolution)', on Wed, 2 Mar 2005:

But will it wake you up within four clock cycles?

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Mac wrote:

Your algorithm also accumulates error and your mistake is to fix the AB condition at which you make an increment/decrement decision. I have included what I believe to be 'a' Verilog specification of a working machine that expands upon your original idea- but one never knows when using online Verilog "manuals" written by !@#$%^& imbeciles who wouldn't know precision of expression if it blew up in their face. What is it with this weak language that it has no multidimensional conditional assignments?- can't believe that. To make a long story short: you must expand the 'cnt' register to a 4-bit, the a/b_out variables are now a function of the msb two bits per your original formulation, the lsb two bits bidirectionally count transitions on the AB state with increments on CW rotation and decrements on CCW rotations. The lsb two bits naturally over/under-flow into the two msb bits of cnt modulo 4, everything stays modulo 4, all motion is accumulated modulo 4 by cnt at each encoder boundary crossing. At any instant cnt[3,2] contains the modulo-16 sum of the net total of CW - CCW encoder increments off its state when quad-div was 'rst', cnt[1,0] is the modulo-4 sum of this total, and cnt[3,2] is the modulo-4 sum of the cnt[1,0] over/underflows. So that mathematically you will have CW-CCW= q*4 + r where r=0,1,2, or 3 , and q=q'*4+r' where r'=0,1,2, or 3. Then CW-CCW=q'*16+r'*4+r so that CW-CCW MOD 16= r'*4+r. The content of cnt[1,0] is obviously r, and the total number of overflows into cnt[3,2] from cnt[1,0] is obviously q, so that cnt[3,2] contains q MOD 4 or r' making cnt[3,0] binary value r'*4+r or CW-CCW MOD 16 as required. If CW-CCW is negative, CW-CCW=q''*16+r'' where r''=0,1,2,...,15 and q''*16=0 and r=0,1,2,3, with q=q'*4+r', r'=0,...,3, with cnt[3,2]=r' and cnt[1,0]=r. In summary then, the instantaneous state of cnt[3,0] is exactly the net number of signed encoder increments off its arbitrary state at quad_div rst, cnt[1,0] is always the net number of encoder cell signed transitions off the initial state, and cnt[3,2] is the net number of signed encoder cell groups of 4 or the DIV 4 output sought. This one

*never* slips- *never* accumulates error-*never* delays, and is easily extended to any DIV number except the quadrature output transitions become impractical to compute in the PLD, will have to make that an external register entry of some kind- at any rate you can run this one at arbitrarily high speeds without limitation. If you want direction outputs then set CW=1 whenever you do a cnt

You and some other people around seem oblivious to the fact the divided output is the integration of the high resolution encoder total angular displacement off an arbitrarily set zero point, and because it is an integration there will generally be no instantaneous reversal. If direction is a required output then make that separate from the divided AB outputs. Because your machine can only make transitions at the A positive edge- you are not integrating anything- your output is unusable when direction changes- there is absolutely no basis in reality for what you've done- all you've got is a bit generator that puts out quadrature codes in steady state.

Let's take this one step further and duplicate the performance of that DigitalControls divide by user selected N for N=1 to 4096 or a 12-bit divisor, with quadrature outputs at "exactly" 50% each. The PLD running off of a high speed external clock makes this very easy. The way to achieve 50% duty at arbitrary divide ratios is to note that the actual divide of encoder resolution cell transitions is 4xN which happens to be Nx4, so that by counting these transitions in 4 groups of N, you naturally end up with your processed encode output using the rule that a_out is high during the 1st and 2nd N-group count, and b_out is high during the second and 3rd N-group count, both a_out and b_out low during

4th N-group count. The simplest conceptual implementation of this would be a bidirectional counter that counts between states 1 and N inclusively where overflow out of state N is to state 1, and underflow from state 1 is to state N. The accumulator functions as before totaling out to the net CW-CCW resolution cell travel off the reset zero point. A simple state machine in a_out, b_out transitioning on these counter over/under-flows then produces the required outputs. I am assuming the use of these so-called "non-blocking" state assignments in Verilog, and this works out nicely even in the usually degenerate case of N=1 which is no problem in a machine working from a much higher frequency external clock. The state machine logic on a_out,b_out is then simply a_out