Stupid 4024 freq divider question (shaft encoder resolution)

I read in sci.electronics.design that Larry Brasfield wrote (in ) about 'Stupid 4024 freq divider question (shaft encoder resolution)', on Sat, 26 Feb 2005:

I suppose you could describe the British Labour Party as a general purpose positioning system, but maybe 'posturing system' would be more accurate. (;-)

--
Regards, John Woodgate, OOO - Own Opinions Only. 
The good news is that nothing is compulsory.
The bad news is that everything is prohibited.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk

Your assumption is correct. A and B are low when I haven't explicitly stated that they are high.

And even so, A and B are obviously NOT in antiphase. The "count" scheme was described in a previous post in this thread. It is NOT a simple counter, but a state machine which can count up or down depending on what the A and B inputs are doing.

Here is a possible cycle of sequential states:

count| a_out | b_out

00 | 1 | 0 01 | 1 | 1 10 | 0 | 1 11 | 0 | 0 00 | 1 | 0 01 | 1 | 1

And so on. Do you now agree that a_out and b_out are in quadrature given the shown progression of count?

There IS a problem with my verilog (which you snipped) but it has to do with back-and-forth transitions. For example, if the shaft is manipulated back and forth in the right place, the count can increase without bound. This will make the output incorrect. But this can be fixed simply by changing the way count is calculated. If I am not too lazy, I will post such a fix later.

The OP won't be reading again until Monday, IIRC.

--Mac

clk was discussed earlier in the thread. It is a normal digital clock which is much faster than the quadrature inputs.

--Mac

You haven't denigrated it. You just said it was incorrect. I'm pretty sure it is only because you didn't read enough context. For the record, clk is a normal digital clock which is much faster than the encoder period. The OP said the encoder signals are in the kHz range, so clk could be 10 MHz or something.

I didn't feel like simulating it because it is NOT MY PROBLEM and I have real work to do in addition to messing about on usenet. Although I guess I got sucked in here, didn't I. ;-)

--Mac

"Randy MacKenna" schreef in bericht news: snipped-for-privacy@f14g2000cwb.googlegroups.com...

Randy,

Your quadrature signals looks like this:

___ ___ ___ ___ ___ ___ ___ ___ A | |___| |___| |___| |___| |___| |___| |___| | ___ ___ ___ ___ ___ ___ ___ __ B __| |___| |___| |___| |___| |___| |___| |___|

When you turn the one direction, and

___ ___ ___ ___ ___ ___ ___ ___ A | |___| |___| |___| |___| |___| |___| |___| | __ ___ ___ ___ ___ ___ ___ ___ __ B |___| |___| |___| |___| |___| |___| |___| |___|

when you turn the other direction.

Repeating on a smaller scale, along with the signals you want to make: _ _ _ _ _ _ _ _ _ _ _ _ _ A | |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| _ _ _ _ _ _ _ _ _ _ _ _ _ B _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| _______________ _______________ X | |_______________| |_______ _______________ _______________ Y ________| |_______________| |

For the one direction - let's say clockwise - and

_ _ _ _ _ _ _ _ _ _ _ _ _ A | |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| _ _ _ _ _ _ _ _ _ _ _ _ _ B |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| _______________ _______________ X | |_______________| |_______ ________ _______________ Y |_______________| |______________

for the other, so counter clockwise.

As you know about state machines, suppose you run a counter using A as a clock in the following sequence, known as Gray code:

000 001 011 010

--
110
111
101
100
000
001
011
010

Mac, Thanks so much for taking the time to post your code. The approach makes sense to me, athough I admit I'm fuzzy on the details. I will continue to work on this until I'm convinced that I understand it well enough to move on it. It's not clear to me how to generate quadrature-offset pulses, but I need to spend more time looking at it. For example, in your case statements, I don't see how a_out and b_out are offset by 90 degrees (or 1/4 pulse width). Maybe they need to be synched to clocks that are already offset?

To the others that contributed to this thread: First, I'm sorry I caused an argument - that wasn't my intention by a long shot. Second, the other suggestions that I do this resolution reduction (or speed increase) using mechanical methods - this would either introduce unacceptable high cost to the project or added backlash (or both).

The suggestion that I contact USDigital for a new optical disk for my encoders would have been a good one -- except I'm not using USDigital encoders. I'm using a set of old encoders off an X-Ray positioning system. Replacement disks are not available.

Thanks, Randy

Don't worry about the argument. You didn't start it. You just provided a forum for it to continue, and if you hadn't, the argument or a similar one would have happened anyway.

My outputs are only approximately in quadrature, because I have synchronized all inputs and outputs to the clk frequency. This clk signal is intended to be, say, a 10 MHz clock.

I don't think this would cause any problems. Afterall, the period of a

10 MHz clock is only 100 nS, and a delay of a few hundred nanoseconds shouldn't cause any problem for an encoder running in the KHz range.

Here is the basic idea:

__ __ __ __ __ __ __ __ __ __ _ a_in _| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| __ __ __ __ __ __ __ __ __ __ b_in __| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__

cnt 0 1 2 3 0 1 2 3 0 1 2 __________ __________ __________ a_out |____________| |____________| |_____ ___________ ___________ __________ b_out ____| |___________| |___________|

If the encoder is rotating in the other direction, everything is the same, but swapped left to right, which is exactly what we want.

The rule for calculating a_out is: a_out is high when count is 0 or 1, and low otherwise.

The rule for calculating b_out is: b_out is high when count is 1 or 2, and low otherwise.

The rule for calculating cnt is a little bit tricky, so stick with me.

There are four input encoder states:

state | a_in | b_in ======|======|===== i | 0 | 0 ii | 1 | 0 iii | 1 | 1 iv | 0 | 1

As the states progress from 'i' to 'iv' as shown above, the shaft is rotating (let's just say) clockwise. To calculate count, what we want to do is pick one of those transitions and define it as the key transition. For example, we could say that whenever we go from state 'i' to state 'ii', we should increment cnt. Likewise, when we go from state 'ii' to state 'i' we should decrement cnt. Then, if the shaft goes back and forth at the i/ii boundary, count will also go back and forth, and a_out and b_out will behave correctly (that is, as if they were real encoder signals).

So, assuming, once again, that we have some fast clock lying around (10 MHz would probably work fine), I would just sample a_in and b_in every clock period, and look for the transitions mentioned above. These would cause cnt to increase and decrease in the desired way, and a_out and b_out would then track cnt, thus giving the correct output.

Probably there is another way to do this which doesn't involve using a separate clock, but it isn't coming to me immediately, and since this will probably work on a small PLD anyway, why bother trying to screw with it?

Here is another untested verilog module. This one differs from the earlier one because I use a much more sophisticated (and correct) way of calculating cnt, and I changed the outputs so they are no longer clocked, but just depend combinatorially on cnt. Note that cnt is still synchronous to clk.

module quad_div(a_in, b_in, clk, rst, a_out, b_out);

input a_in, b_in, clk, rst; output a_out, b_out;

reg [1:0] cnt; reg a_in_r, b_in_r, a_in_d, b_in_d; // r for register, d for delayed.

assign a_out = ((cnt == 0) || (cnt == 1)); assign b_out = ((cnt == 1) || (cnt == 2));

always @(posedge clk or posedge rst) begin if (rst) begin cnt

For grins, watch a moderneeze devotee draw the symbol for an XOR with more than 2 inputs.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

Cool! Thanks, I will check this out...it looks like a simple/elegant solution.

Mac's is nice, too because I think it could easily be extended to other division factors. Plus, I've been looking for an excuse to 'get back into' programming :-)

-Randy

So is this symbol "moderneeze" for XOR? __ -| | |=1|- -|__|

I would've never guessed ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

Say, what's the difference between this symbol:

__ | | |=1| |__|

....and this one (i.e., I know the first is XOR, but is the second also XOR or something else?) __ |>=| |1 | |__|

Thanks...

-Randy

"Randy MacKenna" schreef in bericht news: snipped-for-privacy@g14g2000cwa.googlegroups.com...

Randy,

You just had a question about electronics. That's why this newsgroup exists. There is some discussion, some argument. Nothing to worry about. Everybody is - or at least should be - responsible for his own contribution.

As for your problem I posted a solution that is much too complicated as it takes eight pulse to make one instead of to take the four you asked for. The latter is much simpler and requires only two ICs. See the schematic below.

A ----------------------+ | | | +----------------------------------+ | | | | __ | FF0 | | __ 1-| | | .---. | X +-| | |=1|-------|D Q|----+---|---- |=1|-----|__| +---|Cl | | | +-|__| | | /Q|o- | | | | '---' | | | | | | | | | | | | | | B | __ | FF1 | | ---+-----------| | | .---. | | Y |=1|------|D Q|--------+---- +-----|__| +---|Cl | | | | /Q|o- | | '---' | | | | | +------------------------+ created by Andy´s ASCII-Circuit v1.24.140803 Beta

Look at my other posting for the details of its inner workings. If you use old LS TTL the SN74LS74 flipsflops can be used, and SN74LS86 XOR gates. I'd go for the newer HCT equivalents.

petrus bitbyter

[snip]

I built it up in PSpice, and fed it a quadrature-encoded signal that changes direction.

It doesn't swap lead-lag at a direction change.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

"petrus bitbyter" schreef in bericht news:qf3Vd.251663$ snipped-for-privacy@amsnews05.chello.com...

Guess I need some sleep. You can do without the inverting gate if you use the inverted output of FF1.

A ----------------------+ | | | +----------------------------+ | | | | __ | FF0 | +----|>=| | .---. | X |1 |-------|D Q|----+---|---- +----|__| +---|Cl | | | | | | /Q|o- | | | | '---' | | | | | | | | | | | | | | B | __ | FF1 | | ---------+-----|>=| | .---. | | Y |1 |------|D Q|--------|---- +-----|__| +---|Cl | | | | | /Q|o-------+ | '---' | | | | | +------------------------+ created by Andy´s ASCII-Circuit v1.24.140803 Beta

petrus bitbyter

Read above as "number of true inputs equals 1", unless it has more than 2 inputs. Then read it as either "XOR with function everybody may understand" or "number of true inputs modulo 2 equals 1".

This is plain old OR, or "number of true input greater than or equal to 1".

I wonder how far logic design would have gotten before the computer age if those symbols had been the norm then. Maybe we would avoided the computer age.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

I read in sci.electronics.design that Jim Thompson wrote (in ) about 'Stupid 4024 freq divider question (shaft encoder resolution)', on Tue, 1 Mar 2005:

It's Europeon, I'm afraid. Nobody likes it except the people who invented it. The different shapes stand out even in highly-reduced diagrams (although the negation circles tend to disappear) but the boxes with symbols inside just become black boxes - very apt!

--
Regards, John Woodgate, OOO - Own Opinions Only. 
The good news is that nothing is compulsory.
The bad news is that everything is prohibited.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk

"Jim Thompson" schreef in bericht news: snipped-for-privacy@4ax.com...

Well, don't shoot at the pianist. It's not my idea but sure, an AND gate is a square or a rightangle with an & in it, an OR with >=1 (although in the mathematical notation wich I have not available in ASCII) a XOR has the =1 like you mentioned already. There are more bright ideas. A triangle in the square represents an amplifier and a hysteresis sign a threshold. I don't have the whole IEC definition but only a small book containing the most important things I had to teach my students at the time. But you have to admit it makes ASCII schematics a lot easier.

As for a three or more input XOR gate, FAIK the number of inputs is not limited. So you can have A XOR B XOR C etcetera with only that one =1 sign in it.

Schematic design packages tend to have two symbol lists. One American style and one European style. I don't have problems with it and it gives a lot of relief work for a lot of very important people :) But being a taxpayer :(

petrus bitbyter

You really need to simulate these algorithms before you post them.

petrus bitbyter wrote: [...snip...]

[...snip...]

Not going to work- this is an accumulator problem and not a combinatorial bit matching- your circuit accumulates error on direction reversals.