SR Latch initialization on bread board.

Had link to a pic of what I currently have, and the capacitor change. It must have been missed though. Here is the link to the current logic I am working with on a bread board.

e:

planation for one or many possible solutions on the race state of a SR Latc h on initialization/power up

uit functions correctly once power is on and the SR latch has been manually used to set the desired initial state.

minate and it bounces back and forth to which state wins. But I cannot seem to find an explanation as to how to set the initial state properly and the n have it function as normal.

Am I missing something as it seems like it should be quite simple, but I h ave not seen a solution I can apply on my board. Either I'm blind and its r ight in front of my face or somehow I have been unable to Google it. Found a LOT of sites explaining the race condition, but no solutions on how to "s et" it.

round through a large cap and series resistor, that way when you boot up th e reset pin will be held low until the cap charges up enough to decouple th e reset pin from ground?

wo NOR gates on a quad input NOR gate IC.

wo NOR gates.. not sure I understand how the reset works in that case. Do y ou know of a chip that has that functionality? Just so I can see it and try to figure out how that relates to what was previously brought up.

of two NOR gates or two NAND gates, if you make it out of NOR gates then y ou must hold your reset pin high until your chip boots up, if you make it o ut of NAND gates you hold your reset low until your chip boots up. Holding the reset pin in this way until your chip powers up could help you always boot up into the same state.

I used a capacitor to slow down one of the paths returning from one nor gat e to the input on the other. Would one use a delayed transistor to hold the reset pin on the latch to ac hieve what you are mentioning?

That's ridiculous. The gates don't come close to satisfying: "Intention is that:

1) On power up neither relay is on 2) On momentary reset relay /w green is activated 3) If at any time trip is closed, green side is off, red is on 4) If reset is hit while trip is still open, nothing happens 5) if trip is open then reset will function and be able to trigger green led 6) At no time will both red and green be active 7) On init neither LED circuit is on "

The most basic logic is wrong. Maybe think about a less challenging project.

led

ct.

Perhaps something is lost in translation. As I have it placed out on a brea d board and it is functioning as required. The only change I had to make wa s the capacitor which as far as I could tell set the initial state of the S R Latch to avoid the race condition.

On a sunny day (Thu, 15 Aug 2013 09:46:27 -0700 (PDT)) it happened snipped-for-privacy@bauld.com wrote in :

Yes I have seen that, but was referring to your text. About the same for the circuit diagram though. :-)

A 1.8UF capacitor on the output of a CMOS gate is not healthy. If will draw a lot of current durring switching

Make the reset circuit on the input side with a POR as suggested

Cheers

Klaus

On Thu, 15 Aug 2013 12:56:43 -0700 (PDT), snipped-for-privacy@bauld.com wrote:

---

1. There's a conflict between "3" and "4". Shouldn't "4" read: "If reset is hit while trip is closed, nothing happens."?
2. The capacitor delay implemented like that isn't a good idea.
3. You don't need extra transistors to drive the LEDs.
4. You don't need the pullups and pulldowns on the logic outputs.
5. This'll get you what you want:

Version 4 SHEET 1 1244 980 WIRE 544 32 512 32 WIRE 672 32 624 32 WIRE 864 32 832 32 WIRE 928 32 864 32 WIRE 976 32 928 32 WIRE 672 64 672 32 WIRE 864 64 864 32 WIRE 976 96 976 32 WIRE 928 112 928 32 WIRE -160 128 -336 128 WIRE 352 128 -160 128 WIRE -336 144 -336 128 WIRE 672 160 672 128 WIRE 864 160 864 128 WIRE 864 160 672 160 WIRE 928 160 864 160 WIRE 448 176 416 176 WIRE 352 192 336 192 WIRE 672 192 672 160 WIRE 976 192 976 176 WIRE 336 208 336 192 WIRE 448 208 448 176 WIRE 336 240 448 208 WIRE 448 240 336 208 WIRE -336 256 -336 224 WIRE 336 256 336 240 WIRE 352 256 336 256 WIRE 448 272 448 240 WIRE 448 272 416 272 WIRE 624 272 448 272 WIRE -560 304 -592 304 WIRE -528 304 -560 304 WIRE -432 304 -464 304 WIRE -368 304 -432 304 WIRE -304 304 -368 304 WIRE 672 304 672 288 WIRE 976 304 976 272 WIRE 352 320 -240 320 WIRE -560 352 -560 304 WIRE -432 352 -432 304 WIRE -304 368 -336 368 WIRE -368 416 -368 304 WIRE 128 416 -368 416 WIRE 544 416 512 416 WIRE 672 416 624 416 WIRE 864 416 832 416 WIRE 928 416 864 416 WIRE 976 416 928 416 WIRE 672 448 672 416 WIRE 864 448 864 416 WIRE -560 464 -560 432 WIRE -432 464 -432 432 WIRE 976 480 976 416 WIRE 928 496 928 416 WIRE -160 544 -160 128 WIRE -128 544 -160 544 WIRE 672 544 672 512 WIRE 864 544 864 512 WIRE 864 544 672 544 WIRE 928 544 864 544 WIRE 128 560 128 416 WIRE 160 560 128 560 WIRE 672 576 672 544 WIRE 976 576 976 560 WIRE -32 592 -64 592 WIRE -336 608 -336 368 WIRE -272 608 -336 608 WIRE -240 608 -272 608 WIRE -128 608 -176 608 WIRE -32 608 -32 592 WIRE 0 608 -32 608 WIRE 352 608 224 608 WIRE 160 624 128 624 WIRE 128 656 128 624 WIRE 128 656 64 656 WIRE 448 656 416 656 WIRE 624 656 448 656 WIRE -272 672 -272 608 WIRE -128 672 -272 672 WIRE 0 672 -32 672 WIRE 352 672 336 672 WIRE -32 688 -32 672 WIRE -32 688 -64 688 WIRE 336 688 336 672 WIRE 448 688 448 656 WIRE 672 688 672 672 WIRE 976 688 976 656 WIRE 336 720 448 688 WIRE 448 720 336 688 WIRE -128 736 -160 736 WIRE 336 736 336 720 WIRE 352 736 336 736 WIRE 448 752 448 720 WIRE 448 752 416 752 WIRE -336 800 -336 608 WIRE 352 800 -336 800 WIRE -336 848 -336 800 WIRE -336 960 -336 928 FLAG 672 304 0 FLAG 672 688 0 FLAG -432 464 0 FLAG -336 256 0 FLAG -336 960 0 FLAG 512 32 +12 FLAG 512 416 +12 FLAG -592 304 +12 FLAG 832 32 +12 FLAG 832 416 +12 FLAG -560 464 0 FLAG 976 304 0 FLAG 976 688 0 FLAG -160 736 +12 SYMBOL Digital\\or 384 96 R0 WINDOW 3 -8 36 Invisible 2 SYMATTR InstName A1 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMBOL sw 976 192 M180 WINDOW 0 45 44 Left 2 WINDOW 3 41 70 Left 2 SYMATTR InstName K1 SYMBOL nmos 624 192 R0 SYMATTR InstName M2 SYMATTR Value IRF6617 SYMBOL Digital\\or 384 352 M180 WINDOW 3 -8 128 Invisible 2 SYMATTR InstName A2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMBOL diode 880 128 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL LED 656 64 R0 WINDOW 0 -25 -4 Left 2 WINDOW 3 -101 66 Left 2 SYMATTR InstName D2 SYMATTR Value NSCW100 SYMBOL Digital\\or -272 272 R0 WINDOW 3 -8 36 Invisible 2 SYMATTR InstName A5 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMBOL cap -464 288 R90 WINDOW 0 -32 31 VBottom 2 WINDOW 3 -32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 10n SYMBOL res -448 336 R0 WINDOW 0 -42 42 Left 2 WINDOW 3 -64 72 Left 2 SYMATTR InstName R1 SYMATTR Value 1meg SYMBOL voltage -336 128 R0 WINDOW 0 -106 27 Left 2 WINDOW 3 24 96 Invisible 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value PULSE(0 12 1 10u 10u .1 1) SYMBOL sw 976 576 M180 WINDOW 0 45 44 Left 2 WINDOW 3 41 70 Left 2 SYMATTR InstName K2 SYMBOL diode 880 512 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D3 SYMATTR Value 1N4148 SYMBOL res 640 16 R90 WINDOW 0 -37 59 VBottom 2 WINDOW 3 -33 59 VTop 2 SYMATTR InstName R2 SYMATTR Value 510 SYMBOL res 640 400 R90 WINDOW 0 -33 60 VBottom 2 WINDOW 3 -34 62 VTop 2 SYMATTR InstName R3 SYMATTR Value 510 SYMBOL nmos 624 576 R0 SYMATTR InstName M1 SYMATTR Value IRF6617 SYMBOL LED 656 448 R0 WINDOW 0 -25 -3 Left 2 WINDOW 3 -101 66 Left 2 SYMATTR InstName D4 SYMATTR Value NSCW100 SYMBOL voltage -560 336 R0 WINDOW 0 -70 55 Left 2 WINDOW 3 -68 90 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value 12 SYMBOL Digital\\or 384 576 R0 WINDOW 3 -8 36 Invisible 2 SYMATTR InstName A3 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMBOL Digital\\or 384 832 M180 WINDOW 3 -8 128 Invisible 2 SYMATTR InstName A4 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMBOL voltage -336 832 R0 WINDOW 0 -84 28 Left 2 WINDOW 3 24 96 Invisible 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value PULSE(0 12 2.5 10u 10u 5) SYMBOL res 960 176 R0 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL res 960 560 R0 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL Digital\\and -96 512 R0 WINDOW 3 16 52 Invisible 2 SYMATTR InstName A7 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMBOL Digital\\inv -240 544 R0 WINDOW 3 0 0 Invisible 2 SYMATTR InstName A8 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMBOL Digital\\and -96 768 M180 WINDOW 3 16 52 Invisible 2 SYMATTR InstName A6 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMBOL Digital\\and 32 704 M180 WINDOW 3 16 52 Invisible 2 SYMATTR InstName A9 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMBOL Digital\\or 192 656 M180 WINDOW 3 -8 128 Invisible 2 SYMATTR InstName A10 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V TEXT 520 840 Left 2 !.model SW SW(Ron=.01 Roff=1G Vt=6 Vh=0) TEXT 560 96 Left 2 ;GREEN TEXT 592 480 Left 2 ;RED TEXT -464 184 Left 2 ;RESET TEXT -432 888 Left 2 ;TRIP TEXT 520 872 Left 2 !.tran 10 startup TEXT 528 808 Left 2 ;J Fields 16 August 2013 TEXT 528 768 Left 3 ;INHIBITED LATCH

-- JF

--
Oops... 

Between "4" and "5".

On Fri, 16 Aug 2013 08:21:38 -0500, John Fields wrote:

--- Snipped erroneous circuit list; this one should be OK:

Version 4 SHEET 1 1244 1100 WIRE 544 32 496 32 WIRE 672 32 672 0 WIRE 672 32 624 32 WIRE 688 32 672 32 WIRE 752 32 688 32 WIRE 800 32 752 32 WIRE 496 64 496 32 WIRE 688 64 688 32 WIRE 800 96 800 32 WIRE 752 112 752 32 WIRE -192 128 -336 128 WIRE 176 128 -192 128 WIRE -336 144 -336 128 WIRE 496 160 496 128 WIRE 688 160 688 128 WIRE 688 160 496 160 WIRE 752 160 688 160 WIRE 272 176 240 176 WIRE 176 192 160 192 WIRE 496 192 496 160 WIRE 800 192 800 176 WIRE 160 208 160 192 WIRE 272 208 272 176 WIRE 160 240 272 208 WIRE 272 240 160 208 WIRE -336 256 -336 224 WIRE 160 256 160 240 WIRE 176 256 160 256 WIRE 272 272 272 240 WIRE 272 272 240 272 WIRE 448 272 272 272 WIRE -560 304 -592 304 WIRE -528 304 -560 304 WIRE -432 304 -464 304 WIRE -368 304 -432 304 WIRE -304 304 -368 304 WIRE 496 304 496 288 WIRE 800 304 800 272 WIRE 176 320 -240 320 WIRE -560 352 -560 304 WIRE -432 352 -432 304 WIRE -304 368 -336 368 WIRE 544 416 496 416 WIRE 672 416 672 384 WIRE 672 416 624 416 WIRE 688 416 672 416 WIRE 752 416 688 416 WIRE 800 416 752 416 WIRE 496 448 496 416 WIRE 688 448 688 416 WIRE -560 464 -560 432 WIRE -432 464 -432 432 WIRE 800 480 800 416 WIRE 752 496 752 416 WIRE -192 512 -192 128 WIRE -64 512 -192 512 WIRE 496 544 496 512 WIRE 688 544 688 512 WIRE 688 544 496 544 WIRE 752 544 688 544 WIRE 48 560 0 560 WIRE -368 576 -368 304 WIRE -64 576 -368 576 WIRE 496 576 496 544 WIRE 800 576 800 560 WIRE 176 608 112 608 WIRE 48 624 0 624 WIRE 0 656 0 624 WIRE 272 656 240 656 WIRE 448 656 272 656 WIRE 176 672 160 672 WIRE 160 688 160 672 WIRE 272 688 272 656 WIRE 496 688 496 672 WIRE 800 688 800 656 WIRE 160 720 272 688 WIRE 272 720 160 688 WIRE 160 736 160 720 WIRE 176 736 160 736 WIRE 272 752 272 720 WIRE 272 752 240 752 WIRE -336 800 -336 368 WIRE 0 800 0 720 WIRE 0 800 -336 800 WIRE 176 800 0 800 WIRE -336 848 -336 800 WIRE -336 960 -336 928 FLAG 496 304 0 FLAG 496 688 0 FLAG -432 464 0 FLAG -336 256 0 FLAG -336 960 0 FLAG 672 0 +12 FLAG -592 304 +12 FLAG -560 464 0 FLAG 800 304 0 FLAG 800 688 0 FLAG 672 384 +12 SYMBOL Digital\\or 208 96 R0 WINDOW 3 -8 36 Invisible 2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMATTR InstName A1 SYMBOL sw 800 192 M180 WINDOW 0 45 44 Left 2 WINDOW 3 41 70 Left 2 SYMATTR InstName K1 SYMBOL nmos 448 192 R0 SYMATTR InstName M2 SYMATTR Value 2N7002 SYMBOL Digital\\or 208 352 M180 WINDOW 3 -8 128 Invisible 2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMATTR InstName A2 SYMBOL diode 704 128 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL LED 480 64 R0 WINDOW 0 -25 -4 Left 2 WINDOW 3 -101 66 Left 2 SYMATTR InstName D2 SYMATTR Value NSCW100 SYMBOL Digital\\or -272 272 R0 WINDOW 3 -8 36 Invisible 2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMATTR InstName A5 SYMBOL cap -464 288 R90 WINDOW 0 -32 31 VBottom 2 WINDOW 3 -32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 10n SYMBOL res -448 336 R0 WINDOW 0 -42 42 Left 2 WINDOW 3 -64 72 Left 2 SYMATTR InstName R1 SYMATTR Value 1meg SYMBOL voltage -336 128 R0 WINDOW 0 -106 27 Left 2 WINDOW 3 24 96 Invisible 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value PULSE(0 12 1 10u 10u .1 3) SYMBOL sw 800 576 M180 WINDOW 0 45 44 Left 2 WINDOW 3 41 70 Left 2 SYMATTR InstName K2 SYMBOL diode 704 512 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D3 SYMATTR Value 1N4148 SYMBOL res 640 16 R90 WINDOW 0 -37 59 VBottom 2 WINDOW 3 -33 59 VTop 2 SYMATTR InstName R2 SYMATTR Value 510 SYMBOL res 640 400 R90 WINDOW 0 -33 60 VBottom 2 WINDOW 3 -34 62 VTop 2 SYMATTR InstName R3 SYMATTR Value 510 SYMBOL nmos 448 576 R0 SYMATTR InstName M1 SYMATTR Value 2N7002 SYMBOL LED 480 448 R0 WINDOW 0 -25 -3 Left 2 WINDOW 3 -101 66 Left 2 SYMATTR InstName D4 SYMATTR Value NSCW100 SYMBOL voltage -560 336 R0 WINDOW 0 -70 55 Left 2 WINDOW 3 -68 90 Invisible 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value 12 SYMBOL Digital\\or 208 576 R0 WINDOW 3 -8 36 Invisible 2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMATTR InstName A3 SYMBOL Digital\\or 208 832 M180 WINDOW 3 -8 128 Invisible 2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMATTR InstName A4 SYMBOL voltage -336 832 R0 WINDOW 0 -84 28 Left 2 WINDOW 3 24 96 Invisible 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value PULSE(0 12 2.5 10u 10u 3) SYMBOL res 784 176 R0 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL res 784 560 R0 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL Digital\\inv -64 720 R270 WINDOW 3 0 0 Invisible 2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMATTR InstName A8 SYMBOL Digital\\and 80 656 M180 WINDOW 3 16 52 Invisible 2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMATTR InstName A7 SYMBOL Digital\\or -32 608 M180 WINDOW 3 -8 128 Invisible 2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 12V SYMATTR InstName A6 TEXT 344 840 Left 2 !.model SW SW(Ron=.01 Roff=1G Vt=6 Vh=0) TEXT 384 96 Left 2 ;GREEN TEXT 416 480 Left 2 ;RED TEXT -464 184 Left 2 ;RESET TEXT -432 888 Left 2 ;TRIP TEXT 344 872 Left 2 !.tran 10 startup TEXT 352 808 Left 2 ;J Fields 16 August 2013 TEXT 352 768 Left 3 ;INHIBITED LATCH

-- JF

On Wednesday, August 14, 2013 1:08:50 AM UTC-4, snipped-for-privacy@bauld.com wrote:

ion for one or many possible solutions on the race state of a SR Latch on i nitialization/power up

and it bounces back and forth to which state wins. But I cannot seem to fi nd an explanation as to how to set the initial state properly and then have it function as normal.

"Intention is that:

1) On power up neither relay is on 2) On momentary reset relay /w green is activated 3) If at any time trip is closed, green side is off, red is on 4) If reset is hit while trip is still open, nothing happens 5) if trip is open then reset will function and be able to trigger green le d 6) At no time will both red and green be active 7) On init neither LED circuit is on "

The only reliable way to initialize is with a POR circuit, any other method is mere wish. Based on your description of the logic and adding features such as POR, haz ard-free non-oscillatory state switching, and eliminating the very real pos sibility of hanging in unwanted states due to the asynchronous switch input s, you end up with the something like shown below. Seems to use quite a lot of real estate for so little functionality, 4x 4001, could have made a boo

-boo, but it's not my project so not going to check it out to the max.

Please view in a fixed-width font such as Courier.

. . SYSTEM FLOWCHART . . -------- . | INIT | -------- . | STATE | |RED=1 | . | RED=0 |--|--------------->|GREEN=1 | Q' | S | R . | | . -----------|----|---- . 0 0 | 0 | X . -----------|----|---- . 0 1 | 1 | 0 . -----------|----|---- . 1 0 | 0 | 1 . -----------|----|---- . 1 1 | X | 0 . -----------|----|---- . . . . Then substitute RED and GREEN S R inputs into . . State Transition Table of System Using NOR-Latch . . Transition Table . . . . RED LATCH Inputs . . \ GREEN . RED \ 0 1 . ----------------------------------------------- . |RED 0->1 |RED 0->1 | . |on TRIP |on TRIP | . 0 | | | . |RED_S=TRIP |RED_S=TRIP | . |RED_R=0 |RED_R=0 | . | | | . | | | . |-------------------------|----------------------| . |RED 1->0 | RED 1->0 | . |on /TRIP*RST | no condition | . 1 | | | . |RED_S=0 | RED_S=0 | . |RED_R=/TRIP*RST | RED_R=1 | . | | | . ------------------------------------------------ . . . then equations can be solved by inspection: . . RED_S=TRIP*/RED . . RED_R=/TRIP*RST*RED + GREEN*RED . . . GREEN Latch Inputs . . \ GREEN . RED \ 0 1 . ---------------------------------------------- . | | | . |GREEN 0->1 |GREEN 1->0 | . 0 |on /TRIP*RST |on TRIP | . | | | . |GREEN_S=/TRIP*RST |GREEN_S=0 | . |GREEN_R=0 |GREEN_R=TRIP | . | | | . |-----------------------|----------------------| . |GREEN 0->1 | GREEN 1->0 | . |on /TRIP*RST | no condition | . 1 | | | . |GREEN_S=/TRIP*RST | GREEN_S=0 | . |GREEN_R=0 | GREEN_R=1 | . | | | . ---------------------------------------------- . . GREEN_S=/TRIP*RST*/GREEN . . GREEN_R=TRIP *GREEN + RED*GREEN . . . . . Final task is to create SR-latch with means to force . latch into 01 state upon application of combina- . torial INIT input. . . . . SR-latch . . ------- . ----|S Q|- . | | . | | . ----|R I /Q|- . ------- . | . INIT-----' . . . . . . --------------------------------------------------- . | ___ | . S |--------\ \ | . | | o-- | . | --/___/ | | . | | | ___ ___ | . | | --\ \ ,-\ \ | . | | | o---| | o--+------------|/Q . INIT |-----|-------------/___/ '-/___/ | | . | | | | . | | | ___ | . | | ---\ \ | . | | | o-+-| Q . R |-----|------------------------------------/___/ | | . | | | | . | | | | . | '-------------------------------------------' | . --------------------------------------------------- . . . . . . . Then instantiate logic with real parts: . . . . . . INPUT SWITCH LOGIC . . . VDD RST MOM . | SW . TRIP o | . SW / --- . o ,------o o--+-----------> /TRIP*RST . | __ | | . | ,-\ \ | | . +-----| | o-+-----------|-----------> /TRIP . | '-/___/ | . | | . | | . +--------------------------|-----------> TRIP . | | . [10K] [10K] . | | . --- --- . com com . . . . . SR-Latch Logic . . . ,------+--------------------, . | | | . | | | . | | ___ GREEN | . __ | -\ \ ------- | . ,-\ \ | | o-|S Q|---+--[4.7K]-->to . /TRIP*RST----| | o--|--------/___/ | | GREEN . '-/___/ | | | relay . | ___ | | drvr . TRIP------------------|-\ \ ___ | | . | | o-\ \ | | . ---|-/___/ | o-|R I /Q|---, . | | -/___/ ------- | . | | | | | . | | | | | . | | | | | . | | '------------|-------' . INIT | | | . from >-------------|---|-------------------+ . POR | | | . | | ,------------|-------, . | | | | | . | | | | | . | | | ___ | | . | | ___ -\ \ ------- | . | -\ \ | o-|R I /Q|---' . | | o-/___/ | | . /TRIP*RST----------|-----/___/ | | . | | | . | ___ | | . /TRIP--------------|------------\ \ | | . | | o-|S Q|---+--[4.7K]--> to . | -/___/ ------- | RED . | | RED | relay . | | | drvr . | | | . '----------+--------------------' . . . . .