Sorry for the OT question to the IC design guys ;-)

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Are you building one board or engineering for mass production? If you are building one board, just buy the real thing and screw simulation. If you are building for mass production, expect headaches since distortion isn't tested.

Basically, you are just fooling yourself to think you are doing actual engineering. Rather, you are just playing a mind game that has no assurance to work in real life Spice is a tool, it is not reality. The results are no better than the model. If you had the actual circuit in spice and the process models, then maybe you have a chance. Usually the design engineer has a family of models to use that represent the spread of the process.

I would contact apps. They often use circuits where the pull extra current from the output (usually Jfet) to bias the output stage more into class A, though it is still AB.

snipped-for-privacy@sushi.com a écrit :

Uh... I didn't disclose all the issues because some unintended eyes could lurk here, but be assured that I don't delude myself. (and also that I'm far far from being a beginner) The circuit in itself works well within specs but some unexpected things happened when loaded. That unexpected distortion coupling mechanism (not internal to the opamp) have been identified, checked against modeling (not necessary saying spice) and a double check experiment have been conducted to confirm it is indeed what's really happening. All the outcomes tally very well with "theory"... Now, where the opamp matters is WRT to its output stage behavior and particularly how the output current is reflected to its supply lines. It's that reflected current, which I first was 'surprised' to discover having surprisingly low H2 levels when compared to a crude half wave rectified sine current (should it be with some pseudo class A enhancement tricks), that have been modeled. Just the output stage - with obviously no intent to have any global distortion figure, which, at the sub tenth of a ppm level, would carry absolutely no meaning...

Several prototypes have been built and work predictably, according to what I've said before. Anyway, the output stage current transfer behavior is of some concern, WRT to production spread, in order to estimate some reliable production margin, and that was the only intent of my original question.

Know all that...

Yup, done.

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I think you over-analyzed my reply. Basically if it is not guaranteed on the datasheet, then the performance is subject to process variations, as long as the part passes final test. I had a part with a typical THD spec, only to find a few years later the THD was 10db higher. This was tracked down to a change in the epi vendor. Hey, who knew?

To go a bit more into the QA flow, and not necessarily specific to Linear Technology, there are three fundamental ways performance is guaranteed . Obviously there is actual testing. Next, there is testing that is GBD (guaranteed by design). In the dark ages, that only referred to say the capacitance at an input pin. Something that you wouldn't waste time testing, or couldn't test on the ATE. GBD has morphed a bit over the years, mostly to cut down on testing over temperature. If you can get the flow out of the factory, they often skip the cold testing (QA sampled usually) since it is expensive and a pain in the ass. In theory, the hot and room temp tests will insure the cold test works. Well that is the theory. The third way performance is assured is a parametric test on the wafer itself. The wafer fab doesn't know the product from a hole in the ground, but they know the characteristics of the process.

Now the parametric test is where things can get ugly. Say a certain device in the test pattern is out of spec. This data is presented to somebody to make the "executive decision" if the product is worthy of test, and also is the parametric problem leads to something that won't be caught in ATE. You might get lucky and that device is not even used in the design. If it is a breakdown spec, the person making the decision would see if it is relevant to the product. The problem is the designer is often long gone, so the job is handed off to either another design engineer (busy with their own work) or a product engineer that may not really understand the product. So maybe the part passes all the ATE but still behave differently from the "normal" part.

The output stage is a place where often there are tests performed not shown the datasheet. For instance, you may put some crude protection circuit into the stage with specs not given, but are such that datasheet parameters are not effected. This is done for a few reasons. One is to make sure the part survives the design-in stage. In prototyping circuits, bad stuff can happen. Scope probes can bridge pins, excess supply voltage may be used, etc. If the part is "touchy", the designer goes elsewhere. These hidden protection circuits are very common on switcher chips, but also on some op amps. Secondly, you like think if the end user abuses the part, it might live. Anyway, without knowing your design, you might find yourself triggering protection circuitry.

I met a systems designer doing military COTS products. The discipline he followed was to take the datasheet and a sharpie. If the spec wasn't tested, he would blot out the line item on the datasheet. Then the question remained could the product work on the parameters actually tested.