A pot or a trimmer cap makes sense. I get pushback from young things that are prejudiced against pots. But really, when testing is making pulses, it would only take them a few seconds to turn a pot to make the pulses look right.
Capactance in the Z direction has a big tempco. Can you do horizontal X or Y on an inner layer?
--sp
-- Best regards, Spehro Pefhany Amazon link for AoE 3rd Edition: http://tinyurl.com/ntrpwu8 Microchip link for 2015 Masters in Phoenix: http://tinyurl.com/l7g2k48
I guess so, except that I'd have to do the math somehow. And I'd have to add vias, which should be OK.
I could do some horizontal stubs or pours on layer 1, to add C across R1. I could measure some hacked proto to get into the ballpark.
I once measured a sheet of copperclad FR4 (z-axis) capacitance at something like 950 PPM/degC, negative I think. Is it less in-plane?
Or use PCB fingers/tracks. Add solder or wire link to connect a finger to give more capacitance. Or cut wire links maybe.
NT
Preset pots are a long term reliability disaster. Perhaps a set of 4 wire links that you cut to get the right C.
NT
Why?
And uncut if you overshoot.
Testing would kill me, and manufacturing would jump on the bones.
Plus it would drift around with temperature and humidity. FR4 is a horrible dielectric.
Cheers
Phil Hobbs
The X-Y CTE is something like 1/5 the Z so I think it should be much less. Just a guess though.
--sp
-- Best regards, Spehro Pefhany Amazon link for AoE 3rd Edition: http://tinyurl.com/ntrpwu8 Microchip link for 2015 Masters in Phoenix: http://tinyurl.com/l7g2k48
I'm not sure why, but experience shows they are. It's why they've fallen out of favour.
I expect all units would want much the same setting
NT
Why? It's standard practice.
NT
If the upper capacitance is partly made with FR4 dielectric you want the lower one to be likewise. Getting them to the same degree should be fun.
NT
I still don't have any idea what the stray C might be. I suppose I
You can do a pretty good job of getting rid of the FR4 contribution by extending the pads and putting big slots under the top resistor. (Extra credit for plating the slots without shorting the resistor.) That helps the leakage, too. It's pretty hard to get all the flux out from under the resistor without using a slot.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Because customers just *love* to twiddle them IME.
-- John Devereux
Pots are fine as long as you don't expect more than about 0.25% longterm stability. In my current situation, I'm just trying to make a pulse look good on a scope, so a few per cent of the pot range would be close enough.
If that were the case, I could just pick the compensation cap value once. Which might be good enough.
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You're right, the problem here is peaking, the opposite of the usual TI amp problem.
Then why not change the 2M divider resistor to 200k? 200K * 4pF = 800nS, problem solved. Make the op-amp stage x10. Or 100k and x20.
Constructing the divider from 500 instances of the same resistor would automatically balance their shunt capacitances according to the divider ratio (and look very silly!).
Cheers, James Arthur
Pots aren't too bad, little presets are
NT
The parasitic shunt cap across the 1G resistor will differentiate the HV rising edge and still make a pulse overshoot. 0.1 pF and 1 Gohms has a tau of 100 usec
I saw an appnote recently, somewhere, for reducing resistor shunt capacitance, by a lot, by filling under the resistor with some topside ground. But that would wreck my high voltage clearance.
I think some people do that trick with multiple series resistors, too.
The worst way to tune a design is by re-etching PC boards. I don't want to do that. A variable cap or an equivalent pot-controlled capacitance would let my test people tweak the step response, independent of PCB variations. People who don't approve of trimmers will whine, but I am The President, after all.
Caddock makes axial thickfilm resistors that have essentially no L or C. One of them can make a high voltage divider, into a 50 ohm scope, that's flat to something like 6 GHz. But I don't think they can do that at 1G ohms. Or in surface mount.
What is a "little preset"?
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1) Yes, it's differentiated and yes it'll overshoot. But the time constant is .1pF and (1G in parallel with 200k), not 1G, so the overshoot is short-live d, and maybe even too small to notice, depending on your slew rate.(The pulse / overshoot is also, technically, not 1,200V, but 1,200V * the capacitive divider ratio between .1pF and ~4pF, or about 1/40th * 1,200V).
But we're talking past each other--I've attached a sim file. Look at the settling time difference between my suggestion V(A) and the original, V(B). V(B_scaled) lets you see the two on the same scale.
2) If it's really .1pF that's horrible; different measures are called for, like a diff amp where a 2nd 1G resistor is a.c.-coupled, and subtracts the 1G resistor's capacitively-coupled current from the output.Cheers, James Arthur
Version 4 SHEET 1 1032 680 WIRE 192 0 -48 0 WIRE 272 0 192 0 WIRE 368 0 272 0 WIRE 448 0 368 0 WIRE 800 0 448 0 WIRE 880 0 800 0 WIRE 272 16 272 0 WIRE 880 16 880 0 WIRE 192 32 192 0 WIRE 368 32 368 0 WIRE 448 32 448 0 WIRE 800 32 800 0 WIRE -48 96 -48 0 WIRE 192 128 192 96 WIRE 272 128 272 96 WIRE 272 128 192 128 WIRE 368 128 368 96 WIRE 448 128 448 112 WIRE 448 128 368 128 WIRE 800 128 800 96 WIRE 880 128 880 96 WIRE 880 128 800 128 WIRE 272 160 272 128 WIRE 272 160 192 160 WIRE 640 160 272 160 WIRE 880 160 880 128 WIRE 880 160 800 160 WIRE 992 160 880 160 WIRE 272 176 272 160 WIRE 880 176 880 160 WIRE 192 192 192 160 WIRE 448 192 448 128 WIRE 448 192 368 192 WIRE 640 192 448 192 WIRE 800 192 800 160 WIRE -48 208 -48 176 WIRE 448 208 448 192 WIRE 368 224 368 192 WIRE 192 272 192 256 WIRE 800 272 800 256 WIRE 272 288 272 256 WIRE 880 288 880 256 WIRE 448 304 448 288 WIRE 640 304 448 304 WIRE 368 320 368 288 WIRE 448 320 448 304 WIRE 448 432 448 400 FLAG -48 208 0 FLAG 272 288 0 FLAG 192 272 0 FLAG 448 432 0 FLAG 368 320 0 FLAG 640 160 A FLAG 640 304 B_scaled FLAG 640 192 B FLAG 880 288 0 FLAG 800 272 0 FLAG 992 160 C SYMBOL voltage -48 80 R0 WINDOW 3 -154 169 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value PULSE(0 1200 0 2uS 2uS 50uS) SYMBOL res 256 0 R0 SYMATTR InstName R1 SYMATTR Value 1G SYMBOL res 256 160 R0 SYMATTR InstName R2 SYMATTR Value 100k SYMBOL cap 176 32 R0 SYMATTR InstName C1 SYMATTR Value .1pF SYMBOL cap 176 192 R0 SYMATTR InstName C2 SYMATTR Value 4pF SYMBOL res 432 16 R0 SYMATTR InstName R3 SYMATTR Value 1G SYMBOL res 432 192 R0 SYMATTR InstName R4 SYMATTR Value 1.9meg SYMBOL cap 352 32 R0 SYMATTR InstName C3 SYMATTR Value .1pF SYMBOL cap 352 224 R0 SYMATTR InstName C4 SYMATTR Value 4pF SYMBOL res 432 304 R0 SYMATTR InstName R5 SYMATTR Value 100k SYMBOL res 864 0 R0 SYMATTR InstName R6 SYMATTR Value 1G SYMBOL res 864 160 R0 SYMATTR InstName R7 SYMATTR Value 100k SYMBOL cap 784 32 R0 SYMATTR InstName C5 SYMATTR Value .1pF SYMBOL cap 784 192 R0 SYMATTR InstName C6 SYMATTR Value 1nF TEXT 30 360 Left 2 !.tran 150uS TEXT 608 384 Left 2 ;15-Nov-2015 jda
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