Short pulser.

Could you be more vague? "Few" is a poor substitute for a requirement.

Pulse rep rate range required? Pulse width range desired? Pulse rise/fall times required? Range of high and low levels desired? Max difference between high and low levels?

IF you keep the rate low enough for the pulse width generator to recover, you should be able to shorten the pulse width of your unspecified generator until the risetime limits the output.

Something like this?

On a good ground plane, with fast gates, you should be able to get under 2 ns width and sub-ns edges. Try NL37WZ16US.

There is supposedly a TinyLogic one-shot, but I don't know much about it.

John

one per second would work.... 1kHz is fine

yeah... 3 to 10 ns

well 1.5 ns will give a 3 ns runt pulse. less is of course better,

If you've got a solution that is only ground to 100mV that would work.

100mV

oted text -

OK.

George H.

Ahh, I'll have to try it. 74AC's have the fastest edges? I've only got 74HC's, but they should still work.

Thanks, I was just drawing pictures of inverted (and delayed) steps swallowing each other in some sort of summer.

OK, at 0.56 for one a digikey it's well under the price limit. Do you keep that number in your head?

OK maybe I'll check.

Thanks again,

George H.

text -

For what you want, it might be interesting to try an avalanche generator. Many transistors avalanche just fine. Use a chunk of coax to set the pulse width and an attenuator go get the signal amplitude down where you want it. Drive it with your existing generator. Should be able to get pulses much shorter than a nanosecond and an amp of drive capability with no effort at all.

Yuk! Slow!

No, but I have it on a card in plain sight, along with my cell phone number and the charge on an electron. My favorite CMOS part. Unfortunately, it's in a US8 package.

Try all three sections in parallel some time. Ferocious.

John

Use an open coax cable for termination; "clips" the pulse to 2X length. About 2.5nSec per foot if i remember right. Note with a "wide" pulse drive, you will see two - one when the pulse gen goes from zero up, and one when it goes back to zero. A shorted line does the same but the generator may not like that. Rise & fall times will be no better than the source.

This sounds like the beam-blanking pulses we needed for our stroboscopic electron microscope.

We generate 0.5nsec, 1nec, 2nsec, and 4nsec by gnerating a longer pulse in 100k ECL - Motorola's ECLinPS is quite a lot quicker, but this was back in the mod-1980's, and feeding it through a tapped delay line built up with appropriate lengths of minature coax. This gave us a set of delayed versions of the same pulse.

The right pair of pulses would then be fed into a discrete NOR gate built with three broadband transistors - BFR92 (NPN) or BFT93 (PNP) organised a long-tailed triple - and the current that came out was the desired pulse.

The amplitude wasn't up to much, but we fixed that with a tolerably expensive HP microwave transistor. If you can live with 100mV, the

10mA you can switch with a BFR92 - 500mV into 50R - would be plenty. We did one variation with BFR96's as output transistors, which never did better than 800psec - we had three pairs of them organised into a Percival distributed amplifier, with three sets of drivers, which might have done better with more tuning, but the HP transistor approach was a lot simpler (if a lot more expensive)and worked first off.

-- Bill Sloman, Nijmegen

Feed your pulse to the input of an inverter and one input of an exclusive-or, and the output of the inverter to the other input of the exclusive-or. The output of the exclusive or should be close to the propagation delay of the inverter.

Good Luck! Rich

A PMOS - Poor Man's One-Shot. ;-)

Cheers! Rich

here is whay I did some yime ago:

using an eclinps D-Flip Flop, the trigger input is CLK, set D=1; tie together Q and CLR . Presto !

for wider pulses add an RC from Q to CLR.

Jure Z.

On a sunny day (Sat, 4 Dec 2010 17:06:17 -0800) it happened "Jure Newsgroups" wrote in :

Yes, way to go, did it 'some time ago' too with TTL: ftp://panteltje.com/pub/fdc-2-cutout.jpg

Jan, yes ! same concept, different technology, different speed.

BTW: sorry for the typo >>here is whay I did some yime ago:

Use a flip/flop and two monostables: trigger sets the flip/flop, after a couple of gate delays same trigger triggers monostable #1 and after a couple more gate delays triggers monostable #2. Then NAND (or whatever fast gate equivalent suits you) Qff * /Qm1 * Qm2 The general idea, is that the monostables have the fastest rise time of the logic you use, but not the shortest pulse time. But, the time difference of two monostables, after one gate delay, can be very small.

You have to reset the flip/flop each cycle, and use the gate delays, to keep the indeterminate edge behavior under control.

Hmm. The only dynamic data I could find in the data sheet is propagation delay.

An alternative would be the Micrel SY99022V

wERNER

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Thanks Jure, That seems simple enough.

George H.

Whit3rd, I'm a bit confused. The gate delays are coming because I've added some buffers (or inverters) to the lines triggering the monostables? Does /Qm1 indicate that I'm Nanding the inverse of Qm1 with the other signals? (That part makes sense I just need clarification on the notation.) And finally what is the purpose of the flip flop? I drew a timing picture of it 'going high' first. But it doesn't seem like the fast edge of the flip flop ever does anything.

Thanks for the idea's though (even if I am confused.)

George H.

If all he wants is a scope blip, ECL would work. Something like an MC10EL89 will put a volt into 50 ohms, with very fast edges. It has differential inputs and behaves like a comparator, so an RC glitcher will drive it fine.

John

What's the flipflop for?

John