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A Short Pulse Catcher

Hello, In

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there is a short pulse catcher circuit, which uses a S-R latch and a D flip-flop. In the given VHDL source code, synthesis_off is used for telling the compiler to not optimize away the latch.

ISE webpack 7.1 can not use this (attribute synthesis_off of A: signal is true;). Without this statement, after synthesis, a warning is given (the following signal(s) form a combinatorial loop: spc_inst_a, spc_inst_n_a.).

Any idea for how to handle synthesis_off and remove the warning? Thanks!

Reply to
Johnschool
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warning is not a problem its just reminding you about comb feedback. It is not advised to model latches as comb logic in fpga as they have a seperate latch primitive for that. but you will have difficulty simulating it.

Reply to
Neo

Hi Neo, Thank you for your reply! Do you know if there is other methods to realize short pulse catcher, so that I can remove the latch and the warning (you are right, the warning doesn't affect the software work, but I still want to remove it. :-)).

Reply to
Johnschool

The Flancter circuit will do it nicely, and IMHO is much more suitable for typical FPGA implementation than your latch thing.

Flancter is an unusual word; Google is your friend :-)

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223          mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                Web: http://www.doulos.com

The contents of this message may contain personal views which 
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Reply to
Jonathan Bromley

Hi Jonathan, Thank you very much for your reply! Your information is very useful to me.

Reply to
Johnschool

Hi Jonathan, I just read the material about Flancter circuit.

Since the short pulse is shorter than one clock cycle, it is impossible to connect the short pulse to SET_CE and RESET_CE. So I have to connect the short pulse to SET_CLK, and the system clock to RESET_CLK. Is this right? Thanks!

Reply to
Johnschool

No, not me; you're mailing to the newsgroup!

I think that's the right idea. I don't have in front of me the document you're reading, so I'm not sure; but I think it's right. The Flancter is a twisted ring-of-2 with separate clocks on the two flops. An active edge on one of the clocks will make the two flops' outputs different; an active edge on the other clock makes the two flops' outputs the same. A simple XOR of the two outputs then tells you which of the two clocks happened most recently. Both flops can have a clock enable, but each enable must be in the clock domain of the corresponding flop's clock. The XOR'd output is an asynchronous signal, and it is sometimes necessary to resynch it back into one or the other clock domain using a traditional resynchroniser circuit.

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223          mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                Web: http://www.doulos.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.
Reply to
Jonathan Bromley

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