Shielding ADC with High CMRR?

That last point is highly relevant. If it were as amazing as you want it to be, they'd have trumpeted it to the skies.

Unfortunately, now that datasheets are owned by the marketing department, you have to read them like Kremlin communiques.

Cheers

Phil Hobbs

Where does the signal ultimately come from? Do you have a differential amp ahead of the ADC? What's the analog bandwidth and sample rate? How noisy is the signal itself?

Will the board be in a nice metal box by itself, or is it exposed to nasties?

Yeah, I don't know about ADC's, but for instrument amps one finds that the CMRRR drops at ~20dB/decade above some low frequency... I'd guess it follows the open loop gain, but I'm not sure.

The pickup will also depends on the input impedance. (Your -60dBm number is for a 50 ohm input?)

George H.

Yep. CMRR is spec'd at some low frequency where it looks good. Back in the days when I gave chip design seminars for ICE, I used to enjoy the faces-turned-white when I reversed the CMRR calculation into effective common-mode GAIN ;-) ...Jim Thompson

ield my 16-bit ADC because it has a differential analog input with a CMRR o f 80 dB. I'm wondering if the CMRR will desensitize the input to any expect ed EMI, which will be common mode because the E-field across the input pin spacing of 0.5mm should be predominantly uniform at expected frequencies. I don't expect any EMI to exceed -60 dBm so 80 dB of CMRR should bury the EM I into the ADC noise floor. Any thoughts? I suppose one problem could be th e frequency-dependent degrading of CMRR, though the ADC datasheet doesn't p rovide an CMRR vs frequency data.

p ahead

ies?

The ADC follows a diff amp, whose input is connected to a balun. I'm planni ng to shield this input circuitry but was wondering if I really needed to e xtend the shielding to include the ADC. Based on the responses I've receive d regarding the frequency-dependent nature of CMRR, I'm now inclined to shi eld the ADC, but I'll first ask the manufacturer if they can provide more d etailed CMRR data.

"common mode GAIN" - yikes!

Here's a 250 MHz 12-bit ADC, with a diff ADC driver ahead of it.

(one of my favorite boards, for several reasons)

It's in a metal box, but has no internal shielding. A couple of switchers and a high-voltage supply are inches from the ADC. Base noise is around 1 LSB RMS.

Noise is usually conducted on the PCB - power rails, pours, ground loops, clock jitter - more than airborne. A shield above the ADC probably won't do much.

What's your sample rate? Clock jitter can dominate the noise floor at wider bandwidths.

We've seen opamps with high-frequency power-supply-rejection gain.

Yep. It's not unusual for a typical OpAmp to have a common-mode gain of +20dB... 100dB open-loop gain, 80dB CMRR = +20dB CM gain. ...Jim Thompson

Yup. CMR and PSR are input-referred, so you can easily get gain from the rail to the output. Another of those traps for young players.

Cheers

Phil Hobbs

CMRR is more a matter of balance (matching) of components, plus knowing where to cascode devices to improve the spec.

Now it sort of looks like it follows open loop gain only because the mismatch shows up as a differential signal, which in turn gets amplified by the open loop gain.

The impedance of the current source feeding a long tail pair is a classic case where cascoding can improve CMRR simply by not modulating the current in the long tail pair with the common mode stimulus.

A lady application engineer from TI presented a seminar session on 'proper' PCB layout. She went from terrible, using two sided board to 4 layer bd, layout bypassing technique etc. each step she'd ask the attendees, "Is this enough for my 16 bit ADC?" She stopped at what looked like a rather simple 4 layer PCB layout, that was just done well, announcing that that layout gave less than 1 LSB noise.

No mention of shielding over the ADC at all.

For what it's worth I've seen unshielded 24 bit ADC's mounted INSIDE a PC! which demonstrate lower than 1-2LSB's of noise. Tht kind of makes your problem seem trivial, eh?

shield my 16-bit ADC because it has a differential analog input with a C MRR of 80 dB. I'm wondering if the CMRR will desensitize the input to any expected EMI, which will be common mode because the E-field across the i nput pin spacing of 0.5mm should be predominantly uniform at expected fre quencies. I don't expect any EMI to exceed -60 dBm so 80 dB of CMRR shoul d bury the EMI into the ADC noise floor. Any thoughts? I suppose one prob lem could be the frequency-dependent degrading of CMRR, though the ADC data sheet doesn't provide an CMRR vs frequency data.

er' PCB layout. She went from terrible, using two sided board to 4 layer bd, layout bypassing technique etc. each step she'd ask the attendees, "I s this enough for my 16 bit ADC?" She stopped at what looked like a rathe r simple 4 layer PCB layout, that was just done well, announcing that that layout gave less than 1 LSB noise.

When I was working at Cambridge Instruments in the mid-1980's, we up-graded a bunch of noise-sensitive two layer boards, that had always been fitted w ith solid aluminium screens under the track side, to four layer boards, wit h solid 5V and 0V planes on the two inner layers. The artwork changes were minimal - the +15V and -15V rails were still distributed on the outside lay ers of the board, though the decoupling capacitors were directly coupled to buried 0V ground plane.

Not only could we leave off the aluminium screens but the board-to-board sh ielding without them was better than it had been with the screened two-laye r baords. Obvious enough when you think about it - a buried layer is closer to the tracks that it is shielding than a bolted on screening plate, so al l the radiating and receiving dipoles are closer together, and the radiator /receiver aerials are correspondingly shorter and less effective.

Any kind of modern DA advertised as intended for ADC apps maintains its DC CMRR out to 10MHz, with only negligible degradation of maybe 10-20dB out to 1GHz. The problem is the DA is only half the equation, maintaining enough matching of the external analog stuff to any degree of accuracy better than even 40dB is a challenge.

Darol Klawetter wrote in news: snipped-for-privacy@googlegroups.com:

Sorry for intrusion, I am here to learn. Why your 16 bit ACD has an analog input CMRR of 80 dB instead of 96 dB? 80 dB doesn't even reach quantization noise of a 14 bit ADC.

Mass

--- news://freenews.netfront.net/ - complaints: snipped-for-privacy@netfront.net ---

Because it's low end?

Jamie

Because the unintentional common mode input is supposed to be much smaller than the intended differential input signal, ideally zero, but that is not practical so some CMRR is required. To keep the effect of common mode below quantization noise here the common mode must be at least 16 dB below the differential signal at whatever frequency CMRR is specified at, probably more at higher frequencies. A good data sheet would have CMMR vs frequency data.

Presumably Jamie forgot the smiley, sarcasm may not be what you wanted to learn about, although this NG is a good place for that :-).

Regards, Glen

That is generally due to not balancing parasitic capacitance in the layout. Often chips have dummy devices just to keep the capacitance on differential nodes balanced so that no common mode signal is induced due to mismatch in coupling.

There are things in the layout that do not show up in the schematic. That is what can be tricky in analog design.

I bet you have seen LDOs with power supply gain too. Lots of junky companies out there making cheap CMOS LDOs with no clue about analog design. The only thing saving their asses is the capacitance on the LDO output hides a lot of the bad engineering.