CMRR

Hi,

I'm designing a precise Mains Energy Meter (Class 0.2). There's a mandatory requirement in the design spec

  • .. shall detect the homopolar (Phase-Neutral) current in range (10mA ... 30mA) with 10% accuracy

In this Spice implementation I expected CMRR of the circuit should be

60dB or so ... When i compare V_Common_mode and Vout with FFT, the 5KHz is far that attenuation although the 50Hz Carrier is canceled.

Don't understand, the AD8605 has a comfortable open-loop gain/bandwith, Please someone could explain me.

Version 4 SHEET 1 1956 680 WIRE -608 -288 -688 -288 WIRE -432 -288 -608 -288 WIRE -320 -288 -432 -288 WIRE -240 -288 -320 -288 WIRE -96 -288 -160 -288 WIRE 48 -288 -96 -288 WIRE 176 -288 48 -288 WIRE 304 -288 256 -288 WIRE -432 -240 -432 -288 WIRE -96 -240 -96 -288 WIRE -608 -160 -608 -288 WIRE 192 -160 192 -176 WIRE -688 -144 -688 -288 WIRE 48 -144 48 -288 WIRE 160 -144 48 -144 WIRE -432 -128 -432 -160 WIRE -432 -128 -544 -128 WIRE 304 -128 304 -288 WIRE 304 -128 224 -128 WIRE 352 -128 304 -128 WIRE -96 -112 -96 -160 WIRE -16 -112 -96 -112 WIRE 160 -112 48 -112 WIRE -432 -96 -432 -128 WIRE -96 -80 -96 -112 WIRE 192 -80 192 -96 WIRE -16 32 -16 -112 WIRE 176 32 -16 32 WIRE 224 32 224 0 WIRE -688 48 -688 -64 WIRE -608 48 -608 -80 WIRE -608 48 -688 48 WIRE -432 48 -432 -16 WIRE -432 48 -608 48 WIRE -320 48 -432 48 WIRE -256 48 -320 48 WIRE -96 48 -96 0 WIRE -96 48 -176 48 WIRE 48 48 48 -112 WIRE 48 48 -96 48 WIRE 448 64 448 -16 WIRE -544 80 -544 -128 WIRE 112 112 112 96 WIRE 176 128 176 32 WIRE 176 128 144 128 WIRE -16 144 -16 32 WIRE 80 144 -16 144 WIRE 224 160 224 112 WIRE 224 160 144 160 WIRE 112 192 112 176 WIRE 448 192 448 144 WIRE 224 208 224 160 WIRE 224 320 224 288 WIRE -544 336 -544 160 FLAG 192 -80 0 FLAG 352 -128 out FLAG 448 -16 p3v3 FLAG 224 0 p3v3 FLAG 192 -176 p3v3 FLAG 448 192 0 FLAG -16 -112 mid FLAG -320 -288 Hi FLAG -320 48 Lo FLAG -544 336 0 FLAG 112 192 0 FLAG 112 96 p3v3 FLAG 224 320 0 FLAG -432 -128 V_Common_Mode SYMBOL res 272 -304 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 330K SYMBOL res -80 16 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R2 SYMATTR Value 10K SYMBOL res -80 -144 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R3 SYMATTR Value 10K SYMBOL res 208 128 M180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R4 SYMATTR Value 10K SYMBOL res 208 304 M180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R5 SYMATTR Value 10K SYMBOL res -624 -176 R0 SYMATTR InstName R6 SYMATTR Value {Rburden} SYMBOL current -688 -64 R180 WINDOW 0 24 80 Left 2 WINDOW 3 24 0 Left 2 WINDOW 123 24 52 Left 2 WINDOW 39 0 0 Left 0 SYMATTR InstName I1 SYMATTR Value SINE(0 10u 50) SYMBOL voltage 448 48 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value 3.3 SYMBOL Opamps\\AD8505 192 -192 R0 SYMATTR InstName U1 SYMBOL res -144 -304 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 806 SYMBOL res -160 32 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 806 SYMBOL res -448 -256 R0 SYMATTR InstName R9 SYMATTR Value 10k SYMBOL res -448 -112 R0 SYMATTR InstName R10 SYMATTR Value 10k SYMBOL voltage -544 64 R0 WINDOW 3 24 44 Left 2 WINDOW 123 24 124 Left 2 WINDOW 39 0 0 Left 0 SYMATTR InstName V_Common_Mode SYMATTR Value SFFM(0 1 50 0.8 5000) SYMBOL Opamps\\AD8505 112 80 M0 SYMATTR InstName U2 TEXT 360 -248 Left 2 !.tran 100m TEXT -928 -24 Left 2 !;.step param I_mes 10u 100u 10u TEXT -448 288 Left 2 !;ac dec 200 10 1meg TEXT -1016 -176 Left 2 ;I1 represent a CT 1:2000 ratio TEXT -1240 -208 Left 2 ;I1 Homopolar Current betwenn Ph and Neutral wires TEXT -992 72 Left 2 !.step param Rburden 10 50 10

Reply to
habib
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Two things spring to mind. First is that U1 (AD8605) is running at a very large closed-loop gain (400 or so). Its GBW is 10 MHz, which means that its closed-loop bandwidth is only about 25 kHz.

Second is that U1 isn't actually balanced, so CMR can't be larger than

400 (52 dB). It needs another 330k resistor to common.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

Hmm no ltspice on this 'puter. Can you post a schematic pic somewhere? A sneaky capacitance path somewhere?

George H.

Reply to
George Herold

The burdened CT output is already a nice low-impedance voltage source. By floating it and grounding through the 10K resistors, you are begging capacitively-coupled currents to make big common-mode voltages, which then require a super diffamp to reject.

I'd consider using the CT output single-ended, or at least split the burden and ground the center tap.

--

John Larkin         Highland Technology, Inc 

Science teaches us to doubt. 

  Claude Bernard
Reply to
jlarkin

Yes please joint this url JDBqIEnrSgb_CMRR-I-HOMOPOLAR.pdf

Don't sure if you can reach it from where you are

H
Reply to
habib

According to my MathCad I have a figure 3e3 (3000) of Diff gain around the AD8605, maybe I make some mistakes although I'm quite sure on my figures.

Ok then I'll now see my MathCad computation.

Correct. This is here a major parameter for CMRR performance of my circuit. Nevertheless I don't know how modeling the common mode impedance and nor even knows what is his nature in real life (230/115 VAC Power environment) C, L/C ... ?

Thanks, H.

Reply to
habib

Please

formatting link

Sorry, H

Reply to
habib

The resistors accuracy (0.1%), the temp drifts along with the overall gain are the main parameters for increase CMRR. AFAIK.

John, It should need a symmetrical power supplies (p3v3 and n3v3) for the op amp and overall system, which I'm not allowed to do.

Not sure that symmetrical power supplies could resolve common mode phenomenon. It is really hard to master it in Mains Voltage /Currents measurements.

Thx, H.

Reply to
habib

330k/806 = 409.4

The phase shift will be fairly poorly controlled at 5 kHz--it'll change from unit-to-unit with GBW changes. (GBW also has a tempco, but it's never specified AFAICT.)

JL's your guy for that one.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

Humm ... You're probably right. I will verify that by hands. Thanks.

Reply to
habib

Having no common-mode signal to reject is even better.

Then DC shift the CT up, and bypass it to ground.

AC grounding one end of the CT, or AC grounding the center tap of the burden resistor, kills the common-mode signal. Your model assumes a small common-mode voltage. Your signal is small, and the common-mode noise, with the 10K resistors, could be huge.

I'd suggest some high-frequency rolloff too. Power lines can be nasty.

You might look up the circuits of existing ground-fault detectors. There are dirt-cheap chips available for that, and their data sheets and appnotes could be useful.

--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

where?

Yeah, thanks. You've already got the expert advice. I will note that if you don't get the two channel impedances matched you can turn a differential signal into common mode. I've seen that on the LF end with the two channels AC coupled.

George H. (who thinks first about instrument amps for CMRR)

Reply to
George Herold

AC grounding should be a nice solution. Beside this you're right the homopolar current (the fault current to ground) is (very) small in my design so I should select a CT with less ratio; 1:100 ratio should help. Thanks.

Reply to
habib

I designed and built some prototypes of an electric meter, for Niagra Mohawk, intended for use in India. The project didn't go, but the meter worked. It had inductive power and data transfer, so it could be read out even when the line power was down. We did something similar to GFD, but it was to catch people stealing power, more than for safety. Seems that people in India steal power almost as often as people in New York City.

In NYC, I've heard stories of company X drilling through a wall to steal from Y, and simultaneously vice versa.

Designing an electronic meter that's as good as the old rotating disks is surprisingly difficult. See ANSI C12.

--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

FMY, Inductive power and data transfer was based on NFC or something similar, I guess.

NYC, NYC, ... I want to wake up in a city that never sleeps ! ;-)

Thanks for this Ref. (as EN/IEC 62058-31 and EN/IEC 62058-11)

Best regards, H

Reply to
habib

Please John,

Any comments on my Analog Front End for measuring Mains Voltage/Current (for a Energy Meter Class 0.2/0.2S) is welcomed ... if you have any time for.

formatting link

Thanks, H

Reply to
habib

Pretty quiet just now. :(

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

I just did it my way. It used a dumb-bell shaped ferrite rod, resonated, on both ends. I might still have schematics around somewhere.

--

John Larkin         Highland Technology, Inc 

Science teaches us to doubt. 

  Claude Bernard
Reply to
jlarkin

Same comment as for the GFD sensor: you are floating what could be nice low-impedance signals to make them differential, creating a big common-mode signal, then needing a super differential amp to remove the common mode.

Why not hang one end of the current and potential sensors on neutral? I referenced my entire circuit to neutral and had no differential signals.

See TI data sheet fig 10.2. Minimize or kill common-mode signal before trying to reject it. Even TI is doing it the hard way.

--

John Larkin         Highland Technology, Inc 

Science teaches us to doubt. 

  Claude Bernard
Reply to
jlarkin

In that topology Fig. 102 one shall supply an external -2V5 voltage rail to AVSS with AVDD=2V5 This is probably a clean manner but I prefer avoid to design a symmetrical power supply +2V5/-2V5.

Mine is enabling the internal charge pump with AVDD=3V3, Please see Fig.

105 the one named "Input swings below ground, charge pump is enabled."
Reply to
habib

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