semiconductor drift

That's cool. Table 1 shows typical bipolar opamp drift of 5 nV per month for bipolar opamps. Even if our drift is in our first opamp, it's a lot more than that... more like 100 uV/month.

Later on, they say

"The offset drift over time is low for bipolar input stages, and

parameter is dependent upon the heat and mechanical stress induced on the op amp by the fabrication of the circuit board and the application circuit."

Yeah, die stress could be another mechanism.

How about offset CURRENT drift? ...Jim Thompson

I've not seen undamaged bipolar parts (even really, really crappy ones made with crummy processes) drift anything like that much. And I would have seen it, since we went through many iterations of making really inexpensive thermocouple instrumentation over many, many years. CMOS, yes, it can go wacky, because of ionic contamination, I'm told.

Heck our first products were using an LM709 with custom individual hand-wire-wound resistors for calibration (including offset voltage). The customer couldn't tweak those back into calibration even if they wanted to.

Interestingly we recently bought an ADC box from Data Translation for an experiment and they'd routed out around the voltage reference chips, presumably because of some kind of die stress issue- earlier revisions didn't have it. See page 3/8 here:

Best regards, Spehro Pefhany

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I forgot about die stress.

You mentioned low impedance, so I don't think this is a cause, but I should point out that you can stress the ESD protection device and cause a current leak, but otherwise have an operational part.

The problem I see with your question is you are calling the problem drift, but you haven't been able to observe the offset over continuous time. What you call drift could be a shift, i.e. something that happened suddenly.

This is a customer return. You have to trust the customer didn't use the unit.

alogICs.pdf

-Lasse

Look into ARGT (Accelerated Reliability Growth Testing), which is heat-soak plus thermal cycling to wear things out faster than will be experienced in the field.

The artifice is to set test conditions so they accelerate aging as much as possible, and yet are not so sever as to directly damage the item under test.

The ARGT literature goes deep into the various aging (and thus drift) mechanisms. Google will yield many hits.

Joe Gwinn

On a sunny day (Sat, 6 Dec 2014 07:41:34 -0800 (PST)) it happened Lasse Langwadt Christensen wrote in :

I think that is only value of SMDs changing. The width of the serial pulses does not change at all, and that comes from the micro's clock. The guy sounds like talking rubbish. Could not listen to it all.

Perhaps something as simple as "burn-in" _before_ offset adjustment will relieve the PCB board stresses that are probably the cause of the drift. ...Jim Thompson

_an=

all the timing is from the micros clock, it changes about 1% good luck trying to see the baudrate change 1%

-Lasse

Oh, FFS, I thought it might do that- the URL is about 3 pages long.

Best regards, Spehro Pefhany