Terminate or not?

Edge rates matter more than frequency. A DDR2 interface can have sub-ns edges, so a 50 mm trace can ring. Some (all?) DDR2 drams have internal terminators that you can enable. I'd terminate all clock and control lines for sure; I think you can leave short data lines unterminated, but I'm not sure. There should be appnotes for both the dram chips and for whatever processor or FPGA you are using to talk to them.

Ask at comp.arch.fpga, too.

We recently did a Spartan6-to-DDR2 interface. It almost works.

John

What part didn't work?

Except for some TI DSP to DDR2 designs, I've always just terminated as I've had space to do so. This latest design is really tight on board space though.

Sorry, yes I'm the OP. Different usernames on different PCs.

The hard dram controller core is fairly brain-damaged. There's no way to clear the multiple command and data fifos, so it's hard to be sure what the state is. The only fix is to occasionally do a controller reset, which takes hundreds of microseconds and makes the timing analysis tools barf. We do seem to be able to read and write correctly. You can sort of see the FPGA-to-DRAM connections here:

ftp://jjlarkin.lmi.net/Board51.jpg

The chip we're using, MICRON MT47H64M16HR-3G, has internal terminators.

John

Do you often need to do this controller reset, or is there something out of the ordinary that you're trying to achieve?

Don't all DDR2 have ODT? Are there any QDRII that have ODT?

Let's put it this way..the rise and fall times are VERY fast, representing "mid" to "hi" freq RF, so the answer is ALWAYS terminate.