Scope Trigger for digital scope

Well, it took them a whole sheet of schematic to make an opamp.

An old tunnel diode? Those were fun.

John

Tek produced a series of books about 'scope design a few decades ago. The technology has changed, of course, but the concepts (which is what the series was about) and math have not. You might find these worthwhile.

If this is what you want, then you are working far too hard. You should be able to get an extremely clean, reliable trigger from picking off the incident TDR pulse. You'll need some fast logic, but you should be able to determine some nice clean clocked method for driving the sample/hold that fills in enough points. Assuming that the TDR pulse generation has low enough jitter, you should be able to avoid sample time interpolation entirely. What's the aperture time / jitter spec for the PIC? My WAG is that it's not good enough. If it _is_ good enough, that would be even better...

-frank

I've designed some PLLs that were so unstable they absolutely flied from lock. Prior art.

John

Or, let the clock frequency of the ADC not be related to the input signal[1] and let it land at various times after the trigger just by luck. You have to measure the times you've lucked onto for this to work.

[1] I hereby claim to have invented the Phase Unlock Loop a circuit that ensures that a VCO is not in step with the input.

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kensmith@rahul.net   forging knowledge

Do you really need exact or is very good repeatability what you are after?

repeatability is all that matters here. If it is consistent, I can fix it with software. Thanks for the ideas.

Darrell Harmon

Thanks for all the info you have provided. I have gotten more ideas than I ever expected from this newsgroup. I think I will go with the integrator. The idea to sample the ramp on the second cycle after the trigger is excellent. Hopefully 12.5ns is long enough for it to settle to a decent ramp.

I am making this scope modular. The input and trigger will be modules (think plug in scope), so I can experiment with different techniques. I have much more design work ahead of me, but I hope to get this going soon. I will post a link to the schematics and source code when they are done.

Darrell Harmon

the

settle

modules

going

E-mail me - my address is real - if you are interested in protecting your comparator. The buffering we used wasn't expensive or all that elaborate, it seemed to work, and the circuit details aren't seriously confidential.

I've got gEDA loaded on my old computer, so I could presumably send you a schematic if you were interested. (Linux - as in SuSE 9.1, 9.2 and Mandrake 10.1 - can't find my ADSL modem on my new computer, so I've yet to install gEDA on its Linux partition)

------- Bill Sloman, Nijmegen

I occasionally have lost weekends where I get obscessed with something and spend the whole weekend researching and simulating and stuff. My wife gardens and doesn't mind. One such session examined this problem: given a crystal-clocked pipeline ADC looking at an almost-linear ramp, what's the best strategy to use if we want to compute the ramp start time accurately?

What's the optimum ramp slope? If it's steep and only guarantees one adc sample, you get the highest ADC resolution (picoseconds/LSB) but more noise and ramp curvature. If you use a slower slope and take lots of samples and average them, LSB res is worse but you get to average some noise.

Multi-shot averaging tends to linearize the ramp a bit. If you have the time and compute power, you can use the statistics of multi-shot sampling to determine ramp linearity and apply math corrections.

I have a simulator I wrote somewhere around here. The actual problem went away, thank goodness.

Making an electrically clean, fast, linear ramp is another issue. Everything else equal, slower ramps are inherently more linear. But they're, um, slower.

Keep the layout tight and have fun!

John

Things like that have been done, like the HP 5371 modulation-domain analyzer; it fired two ADCs at trigger time, each looking at one of a pair of trapezoidal free-running waveform, sort of a linearized sin/cos. Their patent claims that is the only set of waveforms that can possibly work, and they're wrong.

Thing is, good discrete sample-hold circuits are hard to come by and have all sorts of feedthrough and linearity problems. All the really good s/h circuits are buried inside pipeline ADCs, and that type of ADC needs to be triggered at a constant rate, not randomly when a trigger arrives. So nowadays it's easiest and cheapest to clock the ADC from a good crystal oscillator and have the trigger event make a ramp (or some other waveform) that goes into the ADCs analog input.

A modern integrated pipeline ADC is an astonishing amount of signal processing for the price. 10-bit, 25 MHz parts are just a few dollars;

14 bits at 80 MHz aren't really expensive.

John

There are some simple things you can do if you don't need very fine interpolation. Send the trigger down a tapped delay line and latch the outputs on the clock edge. mike

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There must be a way to do this with a sine wave based on the ADC's clock divided by X. The trigger activates a sample&hold which keeps the value of the sine wave the moment the trigger occured. Digitize this value, do some math (look up table) and you know the time of the trigger in respect to the ADC's clock.

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Did that! It was a real pain to adjust, though.

John